Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 76.2% (11214 out of 14720)
Slice Registers: 52.8% (31101 out of 58880)
Slice LUTs: 54.9% (32336 out of 58880)
DSP48s: 7.3% (47 out of 640)
Block RAMs: 34.0% (83 out of 244)

Timing
---------------------------
40 MHz Onboard Clock: 40.00 MHz (81.43 MHz maximum)
100MHz: 100.00 MHz (104.98 MHz maximum)
125MHz: 125.00 MHz (125.44 MHz maximum)
TS_AdcDataClk: 100.00 MHz (140.53 MHz maximum)
TS_BusClk: 125.00 MHz (126.15 MHz maximum)
TS_SlowBusClk: 33.33 MHz (110.68 MHz maximum)
TS_DramClkDiv100: 100.00 MHz (450.25 MHz maximum)
TS_DramClk200:  MHz (228.15 MHz maximum)
TS_IoRxClock: 250.00 MHz (333.33 MHz maximum)
TS_IoModClipClock0:  MHz (158.78 MHz maximum)
TS_ClockGenXilinxV5x_TxDcm_TxHighSpeedClkDcm:  MHz (291.04 MHz maximum)
TS_ClockGenXilinxV5x_RxDcm_RxHighSpeedClkDcm:  MHz (450.25 MHz maximum)
TS_ClockGenXilinxV5x_RxDcm_RxLowSpeedClkDcm:  MHz (151.91 MHz maximum)

Start Time: 6:35:33 PM
End Time: 10:40:55 PM
Total Time: 04:05:22