Current students

1. Amit Prakash PhD High performance packet classification
2. Sadia Sharif PhD Formal methods in protocol analysis

Former students

1. Sagarika Chalasani MS 2003 A Comparison of Three Scheduling Algorithms for Input-queued Switches
2. Jun Yuan PhD 2002 Enhancing Simulation with Symbolic Algorithms. Motorola, Austin TX
3. Tameen Khan MS 2002 Frame based scheduling. Andiamo, San Jose CA
4. Gaurav Rastogi MS 2001 Stateful Packet Classification. Andiamo, San Jose CA
5. Shashank Gupta MS 2001 Multicast Scheduling for Switches with Multiple Input Queues. Andiamo, San Jose CA
6. Malay Ganai PhD 2001 SIVA: A System for Efficient State Space Search. NEC Research, Princeton NJ
7. I-Min Liu PhD 2000 Algorithms for Physical Design of Integrated Circuits. Silicon Perspective, Santa Clara CA
8. Praveen Yalagandula MS 2000 Guided State Space Search. PhD candidate, CS Department, UT Austin.
9. Tai-Hung Liu PhD 1999 BDD-based Logic Synthesis. Avanti, Fremont CA
10. Padmini Gopalakrishnan MS 1999 Timing Simulation Using Branching Programs. Monterey Design Systems, Sunnyvale CA
11. Rajat Chaudhry MS 1998 Area Oriented Synthesis for Pass Transistor Logic. Intel, Austin TX
12. Ritu Chaba MS 1998 A Toolkit for Verification with Uninterpreted Functions. Qualcomm, San Diego CA
13. Tjahjadi Wongsonegoro MS 1998 Hybrid Techniques for Fast Functional Simulation. Synopsys, Mountain View CA
14. William Hung MS 1997 Better Verification Using Symmetries. Intel, Hillsborough OR
15. Khurram Sajid MS 1997 Symbolic Procedures for a Theory of Equality. Intel, Hillsborough OR