Here is the detailed course descriptor, with a breakdown of prerequisites, lectures, grading policy, test dates, etc. Here are three questions that you can use to check if you are ready for the class.

Please fill out this small bio; it really helps me get to know the class better.

• Class Notes

  I will use, with minor modifications, the excellent notes prepared by David Harris to accompany the text. I've listed the corresponding sections of the book, but you should read more broadly. In particular, I would like you to pay particular emphasis to the "Pifalls and Fallacies" section concluding each chapter.
  • Introduction (1.1-1.3)
  • CMOS Fabrication and its implications (1.3-1.5, 3.1-3.5)
  • Elementary CMOS logic design and layout (1.4-8.7)
  • MOS Devices: Qualitative Picture (2.1-2.3.1, 4.2)
  • MOS Devices: Quantitative Analysis (2.3.2-2.5)
  • Gate design and sizing (We briefly discussed this material, and you are not responsible for the details of logical effort. However, you should know how to formulate minimizing Elmore delay as a function of gate sizes.)
    • Logical Effort (4.3)
    • Combinational Logic (6.1-6.2.1)
  • Interconnect (4.5-4.6)
  • Circuit Families (6.2.2-6.2.5, 6.4-6.6)
  • Adders (10.1-10.2)
  • Sequential Design (7.1-7.5)
  • SRAMs (11.1-11.2)
  • CAMs, ROMs, and PLAs (11.4-11.7)
  • Datapath (10.3-10.10)
  • Test (4.8, 9)
  • MOS Devices in DSM (2.4)
  • Circuit Pitfalls (6.3)
  • Low Power (6, with an emphasis on 6.5)
  • Packaging, Power Supplies, and I/O (12.2-12.4)
  • Scaling and Economics (4.9, and 8.5)

• Sample midterms

  • Midterm 1
  • Midterm 2

• Shouli Yan has a nice detailed derivation for the field induced under the gate; click here for his writeup.

• Teaching Assistants

  • Eric Quinnell quinnell AT sunfire1.ece.utexas.edu, Jiseon Park jpark AT ece.utexas.edu (You can email all the TAs by sending mail to vlsi-ta !at# ece utexas edu_NOSPAM.)

  • Office Hours:

    Mon	-	Xiang 10-noon ENS 142d
    Tue	-	Xiang 2-4 ENS 142d
    Wed	Jiseon 8-10 pm LRC	Eric Q 10-midnite LRC
    Thu	Eric L 2-4 LRC	-
    Fri	Eric L 10-noon	-
    Sat	-	-
    Sun	Jiseon 8-10 pm LRC	Eric Q 10-midnite LRC

  • Eric Quinnell will hold an informal review section each Friday from 2pm-3pm in RLM 6.116. This section is to focus on lecture and hw material ONLY, i.e., lab discussions should be left for office hours.

• Homework

  Here is a first pass at the homeworks. I may add or drop questions; I'm posting them at the start of the semester so you can have some idea of what's coming up. Your solutions should include the reasoning as well as the numerical result.
  • HW1 (Fabrication, Layout): 1.4, 1.8, 1.9, 1.12, 3.3, 3.8 (Due Sep 15, in class.)
    • The TA has scanned the questions for those of you show don't have the book; click here to view them.
    • Here is the solution
  • HW2 (Devices): 2.2, 2.4, 2.6, 2.10, 2.14 (Due Sep 27, in class.)
    • Here is the solution: part 1, part 2, part 3 (correction to noninverting buffer question)
  • HW3 (Performance): 4.2, 4.4, 4.18, 4.24, 4.28 (Due Oct 11, in class)
    • Here is the solution
  • HW4 (Circuit Families): 6.17, 6.26, 6.28, 6.37, 6.40, 6.42 (Due Oct 18, in class)
    • Here is the solution
  • HW5 (Adders, Interconnect): 10.2, 4.30, 4.34
    • Ex 10.2: Change the last sentence to: " ... function of the most significant bits of the 2 inputs and the output."
    • Note that there is an errata for the book here; thanks to Huzefa Sanjeliwala for the pointer.
    • Here is the solution

  • HW6 (Sequential Design, Memories): 7.2, 7.4, 7.10, 11.2, 11.12, 11.13 (Due Nov 10, in class)
  • HW7 (Datapath): 10.13, 10.14, 10.18, 10.19, 10.22
  • Last year's Midterm 1
  • Last year's Midterm 2

• Design projects

  • Layout: post Sep 13; due Oct 4
  • ALU design: post Oct 6. Part (a) due Oct 25; Part (b) due Nov 1
    • Top 10 problems
  • HDL coding and verification: post Nov 3, due Dec 1

• Term paper

  • Here is a draft describing the term papers.

• Resources

  • Read about the latest trends in VLSI design at EE Times; Deepchip.com is a great resource for VLSI CAD. The verification guild focuses on design verification.
  • Steve Rubin's Elextric is a nice public domain tool for VLSI design. He re-wrote it in Java recently, and it runs nicely on Windoze.
  • Document viewing:
    • Use Aladdin Ghostscript to view postscript on Win95/WinNT.
    • Use Adobe Acrobat to view pdf files; you can download Acrobat here
    • You can convert Postscript to PDF via ps2pdf
  • The ECE Learning Resource Center.
  • Getting started with UNIX, vi, g++, gdb.