VLSI1 TA SESSION QUESTIONS THEORY TYPE Q1. Will the back to back connected inverter cause oscillations? Q2. Effect of temp on VTC Q3. What is a symmetric function? Is xor2/xor3 symmetric? Q4. Logical Effort analysis for skewed gates Q5. How does STA engine work? Q6. Why does nand gate has lesser delay than nor gate? Q7. Will inv4 lead to better delay than inv1 always? Q8. What constrains the max fan out in a CMOS logic? Q9. Explain the differences between the Kogge Stone and BK adder. Q10. How does the memory array in Lab1B work? PRACTICAL Q1. hspice reports floating inputs in schematic Check if you are driving all the inputs of your module. Many cases substrate terminal of 4T MOS is found floating. Some naming convention guidelines: A<0> translated to A_0 Do not start pin/net names with digits. Do not use - or: in the pin/net names Q2. What is the best way to do LVS debug? Highlight the errors in the extracted view estimate the region in layout that it corresponds to from neighborhood patterns trace equivalent portions of schematic For small design as in Lab1a 6T SRAM cell full tracing of layout is also not to time-consuming Most common flaws are via missing, substrate/supply connection missing, unintentional shorts in metal layers Q3. How to "write" into memory in Lab1b? This is a read only memory. Use .ic statements for storing/writing data Q4. Common pitfalls in hspice Same source repeated e.g. Vsrc net1 0 dc 1.8V Vsrc net2 0 dc 1.8V Adding statement within subckt definition Q5. Is there any use of coe in Lab2? For this lab it is sort of not used can therefore be left floating. Q6. Some global cure alls when something weird is happening e.g. no netlist produced, too many cadence crashes, vcs is giving strange messages while trying to create executable Check quota for disk usage Clean up current working directory Start from scratch sunapp change between 1/2/3 Change to windows/linux/solaris depending on where you are currently working Check if you have your .cshrc uncorrupted Q.7. cadence crashed and created Edit Locks Move to home directory -> ssh to sunapp -> tcsh -> clsAdminTool -> are ./ -> exit Q8. Invoking vcs/awaves etc. says command not found Add the path settings for the tool from web in .cshrc. Open new terminal -> ssh to sunapp -> tcsh -> Re-invoke tool If you are adding all path settings to some file named e.g. my_cshrc you have to explicitly source it using source /my_cshrc Q9. Will well contact sharing with the PMOS cause DRC violation - why not? No it will not. Q10. I am seeing no change in timing report even after changing my circuit. Check in CIW if it is giving error in trying to netlist Most often the cure is to check and save all sub modules in design starting from leaf level and re-netlisting - in such cases the error signature is cell view XYZ was modified after it was extracted Q11. Make schematic view names as "schematic" only. Do not give view names like schematic_try1, .. Most often it leads to intractable errors in later phase of the design Q12. In pt when I read in design - current design is not remaining the toplevel design and thus timing report is incorrect. Typically it occurs due to some naming convention mismatch workaround is to find the name of the toplevel module from the netlist and rename design in ptnopara.scp and file name for the merged netlist Q13. Make sure that you do not give any cell a name which present as keyword in the perl script mrg2net Open the mrg2net file to understand the reserved keywords. In case you use that your timing arcs will not be traced properly and you will get misleading delay numbers.