- When running the APR tool, the following error occurs:
seultra -m=36 &
***********
CADENCE Program Disaster:
Pseudo color graphics card not detected.
Session aborts.
***********
Solution: You are using a Linux machine. These are not currently equipped graphically to handle Silicon Ensemble. Please use a sun or windows machine.
- A Primetime run results in:
"No constrained paths" or Total Path Delay = 0.0
Solution: You have violated Primetime rules somewhere in your netlist. There is no one answer to this problem, but if you follow these steps, this will disappear.
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Run verilog on your Adder/ALU. After "Start Interactive", but before "Continue", there may be a list of errors or warnings. If any exist, they will kill Primetime. Search for the nets and find the problem.
- Check module names. They may NOT start with numbers (e.g. 16bitadder).
- Check nets that connect to pins at any level of heirarchy. A net name that is different than a pin name will kill Primetime. (e.g. Pin = A<15:0>, wire name = Input<15:0>)
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Your top level name must match all files. Example: Your top Adder is called "MySuperAdder16bit". When you mrgnet2, you must have the -out MySuperAdder16bit. Additionally, in ptnopara.scp, you must set active design to MySuperAdder16bit.
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Check how you generated constant "1"s and "0"s. You may NOT use gnd! or vdd! to do this. (digital design, not analog) It will kill Primetime.
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If none of these work, go to the lowest level of your design and run primetime.
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If this works, move one level higher and run it again. The design that gives you 0.0 is the one with the error.
- APR doesn't work. I get tons of errors when I try to import verilog files.
Solution: Read the webpage very carefully about how to import verilog files. You must import SC018.v first...get out of the import screen...and then import ALU.v .
- Cadence can't import my APR. Am I done with the lab?
Solution: No, you are not. If Cadence can't import your APR layout, skip that step. However, you CAN still run preapr.script and postapr.script Primetime, and are expected to.
- I want to open my APR layout in Silicon Ensemble, but I already did it. What do I open?
Solution: Go to File->Open and look for LBRARY or something of the sort. This is your APR file. Load it.
- How do I generate "0"s and "1"s if I cannot use gnd! and vdd!
Solution: Take any signal and it's compliment and put them into a NAND. Presto!
- I run verilog and try to open the waveform browser to view my results. Nothing happens. What to do?
Solution: The server is crashing. Save your files, and ssh to another sunapp server.
- My design worked yesterday! Now it fails miserably! What happened?
Solution: Type "quota -v" in the terminal. If it says 100000 100000, you've maxed your 100MB quota. This will crash everything.
- Nothing opens, cadence is crashing, errors are abundant, and the tcsh is acting up. What's going on?
Solution: Again, type "quota -v" in the terminal. If it says 100000 100000, you've maxed your 100MB quota.
- What's a good Adder/ALU time?
Solution: It depends on YOUR peers this semester. Ask your neighbor. And don't do a Ripple-Carry.