Lab3 FAQs Can the TXFIFO receive new data immediately after sending one parallel data to the TXLOGIC but before the all the 8 bits of the data has been completely transferred through the serial port SSPTXD? Yes it can. This will lead to more efficient implementation than the one where you wait till full transmission of the data through the serial port. Do we need to stop the ARM clock immediately after the TXFIFO becomes full or we have to wait till the ARM tries to write to a full FIFO? Ideal implementation is to stop the clock if ARM tries to write to a full FIFO. But stopping clock just on the basis of FIFO full condition will not be penalized in this Lab. What happens if ARM tries to write to a FULL FIFO and simultaneously the TXLOGIC tries to get the first parallel data from it? You need to ignore the data which is about to be written since in a synchronous system the SSPTXINTR falls LOW only after a clk2Q delay wrt to the clock edge at which reading by TXLOGIC takes place and consequently any write activity is masked. What is the role played by PHI1 and PHI2? To the external world PHI1 is the important clock and we have to make sure that the data request from the ARM made at one PHI1 rising edge is available to its dataBus port at the next rising edge of PHI1. PHI2 is used for synchronizing some internal state elements of ARM and you have to just ensure that these clocks maintain the frequency and phase relationship as in spec. How do you test synthesizability? Read in all the design modules bottom up from leaf level to top, pass synthesis constraints as mentioned in the web and compile the design. Try to remove all the warnings, esp. with respect to “unmapped components” which implies that some parts of your rtl code cannot be binded to any available library component. There should be absolutely no ERRORs during reading or compilation. How does the memory transfer data when a read request comes? This is handled internally in the mem2.v – where upon any event in the address bus the data from the new address locations is driven on to the databus. How do I handle the shared bus being driven by the SSP as well as the MEMORY module? You can use tristates in the toplevel module where you are hooking up your design, consisting of SSP and Wishbone master & slave, with memory and ARM. Since this module need not be synthesized use of tristateable components is allowed although they are not present in the library. How do I handle blocking and non-blocking assignments? Try to avoid any non-blocking assignments. Make all combinational logic within always@ (*) blocks in stead of using blocking assignment statements. http://www.asic-world.com/tidbits/blocking.html is a good link on how the two constructs fundamentally differ both in simulation and synthesis. What happens if the ARM tries to read a data from the SSP RXLOGIC when the RXFIFO is empty? In a real implementation this should be prevented by telling ARM that it is empty through an interrupt but here assume this at we will not be testing such a condition. A complex implement-tation might handle this by stopping the ARM clocks and inserting wait states till the RXLOGIC gets some data and is in a position to feed it back. My implementation is such that the TXFIFO never gets full using the test program given for LAB3B. How do I show that PHI1 PHI2 are being frozen when TXFIFO is FULL? Write your own test program keeping in mind the clock frequencies you are using and excite the TXFIFO FULL condition. I was maintaining a log of some questions which had not so difficult answers. I am writing down the Qs only. VLSI1 TA SESSION QUESTIONS THEORY TYPE Q1. Will the back to back connected inverter cause oscillations? Q2. Effect of temp on VTC Q3. What is a symmetric function? Is xor2/xor3 symmetric? Q4. Logical Effort analysis for skewed gates Q5. How does STA engine work? Q6. Why does nand gate has lesser delay than nor gate? Q7. Will inv4 lead to better delay than inv1 always? Q8. What constrains the max fan out in a CMOS logic? Q9. Explain the differences between the Kogge Stone and BK adder. Q10. How does the memory array in Lab1B work? PRACTICAL Q1. hspice reports “floating inputs in schematic” Check if you are driving all the inputs of your module. Many cases substrate terminal of 4T MOS is found floating. Some naming convention guidelines: A<0> translated to A_0 Do not start pin/net names with digits. Do not use - or: in the pin/net names Q2. What is the best way to do LVS debug? Highlight the errors in the extracted view – estimate the region in layout that it corresponds to from neighborhood patterns – trace equivalent portions of schematic For small design as in Lab1a “6T SRAM cell” full tracing of layout is also not to time-consuming Most common flaws are – via missing, substrate/supply connection missing, unintentional shorts in metal layers Q3. How to "write" into memory in Lab1b? This is a read only memory. Use .ic statements for storing/”writing” data Q4. Common pitfalls in hspice Same source repeated e.g. Vsrc net1 0 dc 1.8V Vsrc net2 0 dc 1.8V Adding statement within subckt definition Q5. Is there any use of coe in Lab2? For this lab it is sort of not used – can therefore be left floating. Q6. Some global “cure alls” when something weird is happening e.g. no netlist produced, too many cadence crashes, vcs is giving strange messages while trying to create executable Check quota for disk usage Clean up current working directory Start from scratch sunapp change between 1/2/3 Change to windows/linux/solaris depending on where you are currently working Check if you have your .cshrc uncorrupted Q.7. cadence crashed and created Edit Locks Move to home directory -> ssh to sunapp -> tcsh -> clsAdminTool -> are ./ -> exit Q8. Invoking vcs/awaves etc. says “command not found” Add the path settings for the tool from web in .cshrc. Open new terminal -> ssh to sunapp -> tcsh -> Re-invoke tool If you are adding all path settings to some file named e.g. my_cshrc you have to explicitly source it using “source /my_cshrc” Q9. Will well contact sharing with the PMOS cause DRC violation - why not? No it will not. Q10. I am seeing no change in timing report even after changing my circuit. Check in CIW if it is giving error in trying to netlist Most often the cure is to check and save all sub modules in design starting from leaf level and re-netlisting - in such cases the error signature is “cell view XYZ was modified after it was extracted” Q11. Make schematic view names as "schematic" only. Do not give view names like “schematic_try1, ..” Most often it leads to intractable errors in later phase of the design Q12. In pt when I read in design - current design is not remaining the toplevel design and thus timing report is incorrect. Typically it occurs due to some naming convention mismatch – workaround is to find the name of the toplevel module from the netlist and rename design in ptnopara.scp and file name for the merged netlist Q13. Make sure that you do not give any cell a name which present as keyword in the perl script mrg2net Open the mrg2net file to understand the reserved keywords. In case you use that your timing arcs will not be traced properly and you will get misleading delay numbers.