References on Low-Power Design

These references were compiled by Prof. Lizy John, UT Austin.

[Ah96] R. Ahmed and B. L. Evans, "Optimizing Signal Processing Algorithms," Proc. IEEE Asilomar Conf. on Signals, Systems, and Computers, vol. II, pp. 1401-1406, Nov. 3-6, 1996, Pacific Grove, CA.

[Ca92] T. Callaway and E. E. Swartzlander, "Optimizing architecture elements for signal processing," VLSI Signal Processing V, pp. 91-100, IEEE Press, 1992.

[Ch95] A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.

[Ch95b] J.M. Chang and M. Pedram, "Register allocation and binding for low power," Proc. IEEE Design Automation Conf., pp. 29-35, June 1995.

[De95b] S. Devadas and S. Malik, "A survey of optimization techniques targeting low power VLSI circuits," Proc. IEEE Design Automation Conf., pp. 242-247, June 1995.

[Ep] Epic's PowerMill, http://www.epic.com/powermill.html.

[Fo94] G. Forman and J. Zahorjan, "The challenges of mobile computing," IEEE Computer Magazine, vol. 27, no. 4, pp. 38-47, April 1994.

[IRSIM] IRSIM, ftp://sunsite.unc.edu/pub/Linux/apps/circuits/irsim-cap-9.2.linux.tgz

[Im95] S. Imam and M. Pedram, "Logic extraction and factorization for low power," Proc. IEEE Design Automation Conf, pp. 248-253, June 1995.

[HICSS] L. K. John, V. Reddy, P. T. Hulina and L. D. Coraor, "A Comparative Evaluation of Software Techniques for Hiding Memory Latency," Proc. IEEE Hawaii Int. Conf. on System. Science, vol. 1, pp. 229-239, Jan. 3-6, 1995.

[Jo94] L. K. John, B. Choi, P. T. Hulina, and L. D. Coraor, "Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories," Proc. Int. Conf. on Parallel Processing, vol. I, pp. 212-219, Aug. 1994.

[RoJo97] L. Roitberg and E. John, "Voice Recognition Hardware Interface Using Field Programmable Gate Arrays", Proc. ASEE/GSW Conf., 1997.

[Koj95] H. Kojima, D. J. Gorny, K. Nitta, and K. Sasaki, "Power analysis of a programmable DSP for architecture/program optimization," Proc. IEEE Int. Sym. On Low Power Electronics, pp. 26-27, Oct. 9-11, 1995.

[Ko95] U. Ko, P. Balsara, and W. Lee, "Low-power design techniques for high-performance CMOS adders," IEEE Trans. on VLSI Systems, vol. 3, no. 2, pp. 327-332, June 1995.

[La88] M. Lam, "Software pipelining: an effective scheduling technique for VLIW machines," Proc. of SIGPLAN Conf. on Prog. Lang. Design and Implementation, pp. 318-328, July, 1988.

[La95] P. Landman and J. Rabaey, "Architectural power analysis: the dual type bit method," IEEE Trans. on VLSI Systems, vol. 3, no. 2, pp. 173-187, June 1995.

[LaRa96] P. Landman and J. Rabaey, "Activity-sensitive architectural power analysis," IEEE Trans. on Computer Aided Design, vol. 15, no. 6, pp. 571-587, June 1996.

[La96] P. Landman, "High-level power estimation," Proc. of IEEE Int. Sym. On Low Power Electronics and Design, pp. 29-35, Aug. 1996.

[Le95] M. Lee and V. Tiwari, "A memory allocation technique for low-energy embedded DSP software," Proc. IEEE Sym. On Low Power Electronics, pp. 24-25, Oct. 1995.

[Le97] M. Lee, V. Tiwari, S. Malik, and M. Fujita, "Power analysis and minimization techniques for embedded DSP software," IEEE Trans. on VLSI Systems, vol. 5, no. 1, pp. 123-135, March 1997.

[Me97] H. Mehta, R.M. Owens, and M.J. Irwin, "A simulation methodology for software energy evaluation," Proc. IEEE Conf. on VLSI Design, pp. 509-510, Jan. 1997.

[Su94] C-L. Su, C. Tsui, and A. Despain, "Saving power in the control path of embedded processors,'" IEEE Design and Test of Computers, vol. 11, no. 4, pp. 24-31, Dec. 1994.

[Wi96] R. Witek and J. Montanaro, "StrongARM: A high-performance ARM processor," Proc. IEEE Computer Conf. (COMPCON), pp. 188-191, Feb. 25-28, 1996.

[Wu95] S. Wuytack, F. Catthoor, and H. DeMan, "Transforming set data types to power optimal data structures," IEEE Trans. on Computer Aided Design, vol. 15, no. 6, pp. 619-629, Jun. 1995.


Last Updated 06/13/02.