Microprocessors have been the dominant devices in use for general-purpose computing for the last decade, but there is still a large gap between the computational efficiency of microprocessors and that of custom silicon (e.g. DSP and ASICs). Reconfigurable devices, such as FPGAs (basically, reconfigurable ASICs), have come closer to closing that gap, offering a 10x to 100x performance boost. On highly regular, high throughput computations, reconfigurable architectures have a clear superiority to traditional processor architectures. However, in irregular tasks or in those with low throughput requirements, the traditional microprocessor organization is still more efficient than these reconfigurable devices. The best solution, then, could come from combining the two opposite poles: coupling a general purpose microprocessor with a reconfigurable logic array, we could clearly exploit the best of each solution. The very low reconfiguration times that modern FPGAs feature, in particular, are now seriously opening the possibility of a dynamic HW reconfiguration during the execution, adapting the system to the actual computation: the hypotesis is fetching, but a certain number of hurdles have yet to be overcome.
This project will focus on the dynamic HW/SW partitioning problem: using Ptolemy, SDF and the MORPH1 chip that the Politecnico di Milano is developing as reference models, I'll try to develop and implement suitable heuristics to solve the partitioning problem, considering the FPGA dimension, the instructions that can fit in the FPGA (with relative performances) and the relative reconfiguration times.