Freescale DSP56000 Processor

Lecture by Prof. Brian L. Evans

Introduction

The DSP56000 fixed-point DSP uses 24-bit program words and 24-bit data words. It is ideal when the processing requires 17-24 bit data:

high-end digital audio systems quantize audio at 20-24 bits per sample
ADSL and HDSL2 modems require 20-bit coefficients in the adaptive FIR filters for channel equalization

It has two data paths which is useful for stereo audio processing, even though it only has one hardware multiplier unit. It takes two master clock cycles to execute one instruction cycle. Variations of the DSP56000 family include DSP56100, DSP56300, and DSP56600. The DSP56690 decodes any digital baseband communications signal.

The DSP56800 family is a hybrid DSP/microcontroller. One of the earliest applications (mid-1990s) was in speakerphones. In 2004, the DSP56800 finds applications in power control systems:

November 18, 2004, Digital Power Conversion using Freescale 56800/E Hybrid Controllers, On-Demand Presentation by Freescale Semiconductor.

Registers

2 24-bit data registers in each path (x0, x1, y0, and y1). Register x is the concatentation of x1 and x0 and can store 48 bits of an accumulator. Likewise for register y.
8 address registers (r0-r7)

Accumulators

two 56-bit accumulators a and b
- 8-bit extension register (a2 or b2)
- 24-bit most significant word result (a1 or b1)
- 24-bit least significant word result (a0 or b0)
Represent fixed-point numbers between -1 and 0.9999998, inclusive.
Underflow: accumulation produces a number less than -1
Overflow: accumulation produces a number greater than 0.9999998
The extension register offers protection against overflow: it can accurately represent numbers of higher precision and sets the overflow status bit when the other 48 bits are 01111....111.
Overflow protection occurs when an accumulator is written on the X data bus or Y data bus by substituting a limiting constant for the data
Scaling: at input to accumulator, one can shift left by one bit, shift by one bit, no shift, or force to zero the current value of the accumulator
- If we add two unit amplitude sine waves together, how much should we scale the amplitudes before we add them together to prevent overflow and underflow?
  Hint: Consider their maximum amplitude.
- To sum the square of N numbers, e.g. a dot product of a vector with itself, by what number do we have to scale each number to prevent overflow and underflow?
  Hint: Assume each number is -1.
Fairness: algorithm alternates between truncation and rounding to ensure fairness in the least significant bit

Features

The 56000 has the addressing of a conventional DSP processor except bit-reversed addressing. The 56000 has conditional moves to reduce branching. Here is an example of a logical inverter, where 0 is false and not zero is true:

; invert input
        clr     b       input,a          ; b = 0, a = input
        tst     a       #$01,y1          ; test a, set y1 = 1
        teq     y1,b                     ; if a = 0, then b = y1 = 1
        move    b,output                 ; output = b

References

Mohamed El-Sharkaway, Digital Signal Processing Applications with Motorola's DSP56002 Processor, Prentice Hall, ISBN 0-13-569476-0, 1996.
Motorola, Inc., DSP56000 Digital Signal Processing Family Manual, 1992.

Last updated 12/22/04. Send comments to (Mailbox) bevans@ece.utexas.edu