TMS320C6x Very-Long Instruction Word (VLIW) DSP processor

- C6x handout by Berkeley Design Technology, Inc.
- The C6x family consists of the C62x 16-bit fixed-point family and the 67x 32-bit floating-point family. The C6x has six 32-bit adders and two 16 x 16 multipliers which operate in parallel and finish execution in one clock cycle. On the C67x, 32-bit floating-point multiplication requires four cycles (essentially four 16 x 16 multiplications and several additions).
- The C6x family is not a traditional DSP family.
- The C6x does not have a multiply-accumulate instruction. One has to multiply first and accumulate after the multiplication is finished.
- It does not have dedicated hardware units for modulo addressing and bit-reversed indexing; however, two of the adder units support these addressing modes.

- The C6x family are superpipelined processors. On the C62x, fetch, decode, and execute are broken up into 4 cycles, 2 cycles, and 1-5 cycles, respectively, instead of one cycle each. The bad news is that you cannot interrupt a C6x processor if a conditional branch is in the pipeline. The good news is that you can avoid using conditional branches because C6x supports conditional evaluation of all instructions (whereas the Freescale DSP56000 for example only supports conditional moves).
- TMS320C62x has six 32-bit adders and two 16 x 16 multipliers which operate in parallel and finish execution in one clock cycle. fixed-point multiply-accumulate takes two instructions: multiply on one cycle and accumulate on the next. Due to pipelining, one can effectively compute two multiply-accumulates per cycle.
- The following processors have been in volume production in 1999:
- C6201 (1600 MIPS, 400 MMACS, 200 MHz)
- C6202 (2000 MIPS, 500 MMACS, 250 MHz)
- C6211 (low cost, 1200 MIPS, 300 MMACS, 150 MHz) $21 in volume

- Comparison with Pentium MMX processor
- TMS320C67x family is a 32-bit floating-point DSP processor
that is pin-compatible with the TMS32062x
- 32-bit floating point multiplication in four cycles
- C6701 (1 GFLOP, 334 MMACS, 167 MHz, floating-point) sampling today.

Last updated 06/07/22. Send comments to bevans@ece.utexas.edu