/******************************************************************************/ /* DNA PROPRIETARY INFORMATION */ /* (C) Copyright 1997,1998 by DNA Enterprises, Inc. */ /* All rights reserved */ /******************************************************************************/ /* CS4231A Codec Private Include File */ #ifndef _CODEC__H_ #define _CODEC__H_ #define REG_INDEX_OFFSET 0x00 #define REG_DATA_OFFSET 0x04 #define REG_STATUS_OFFSET 0x08 #define REG_IO_DATA_OFFSET 0x0C /* indirect register numbers */ #define IREG_LEFT_ADC_IN_CTRL 0 #define IREG_RIGHT_ADC_IN_CTRL 1 #define IREG_LEFT_AUX1_IN_CTRL 2 #define IREG_RIGHT_AUX1_IN_CTRL 3 #define IREG_LEFT_AUX2_IN_CTRL 4 #define IREG_RIGHT_AUX2_IN_CTRL 5 #define IREG_LEFT_DAC_OUT_CTRL 6 #define IREG_RIGHT_DAC_OUT_CTRL 7 #define IREG_FS_PBACK_DATA_FMT 8 #define IREG_INTFC_CONFIG 9 #define IREG_PIN_CTRL 10 #define IREG_ERR_STATUS_INIT 11 #define IREG_MODE_ID 12 #define IREG_LBACK_CTRL 13 #define IREG_PBACK_UPPER_BASE_CNT 14 #define IREG_PBACK_LOWER_BASE_CNT 15 #define IREG_ALT_FEATURE_EN1 16 #define IREG_ALT_FEATURE_EN2 17 #define IREG_LEFT_LINE_IN_CTRL 18 #define IREG_RIGHT_LINE_IN_CTRL 19 #define IREG_TIMER_LOW_BASE 20 #define IREG_TIMER_HIGH_BASE 21 #define IREG_ALT_FEATURE_EN3 23 #define IREG_ALT_FEATURE_STAT 24 #define IREG_VER_CHIPID 25 #define IREG_MONO_IO_CTRL 26 #define IREG_CAPTURE_DATA_FMT 28 #define IREG_CAPTURE_UPPER_BASE_CNT 30 #define IREG_CAPTURE_LOWER_BASE_CNT 31 /* INDEX address register bits */ #define IA 0 /* Index Address */ #define IA_SZ 5 /* Index Address field width */ #define TRD 5 /* Transfer Request Disable */ #define MCE 6 /* Mode Change Enable */ #define INIT 7 /* CS4231A Initialization */ /* STATUS register bits */ #define INT 0 /* Interrupt Status */ #define PRDY 1 /* Playback Data Ready */ #define PL_R 2 /* Playback Left-Right sample */ #define PU_L 3 /* Playback Upper-Lower byte */ #define SER 4 /* Sample Error */ #define CRDY 5 /* Capture Data Ready */ #define CL_R 6 /* Capture Left-Right sample */ #define CU_L 7 /* Capture Upper-Lower byte */ /* IREG_LEFT_ADC_IN_CTRL (I0) register bits */ #define LAG 0 /* Left ADC Gain */ #define LAG_SZ 4 /* Left ADC Gain field width */ #define LMGE 5 /* Left Mic Gain Enable */ #define LSS 6 /* Left ADC Input Source Select*/ #define LSS_SZ 2 /* LSS field width */ /* IREG_RIGHT_ADC_IN_CTRL (I1) register bits */ #define RAG LAG /* Right ADC gain */ #define RAG_SZ LAG_SZ /* RAG field width */ #define RMGE LMGE /* Right Mic Gain Enable */ #define RSS LSS /* Right ADC Input Source Sel */ #define RSS_SZ LSS_SZ /* RSS field width */ /* IREG_LEFT_AUX1_IN_CTRL (I2) register bits */ #define LX1G 0 /* Left Aux #1, LAUX1, Mix Gain*/ #define LX1G_SZ 5 /* LX1G field width */ #define LX1M 7 /* Left Aux #1 Mute */ /* IREG_RIGHT_AUX1_IN_CTRL (I3) register bits */ #define RX1G LX1G /* Right Aux #1,RAUX1,Mix Gain */ #define RX1G_SZ LX1G_SZ /* RX1G field width */ #define RX1M LX1M /* Right Aux #1 Mute */ /* IREG_LEFT_AUX2_IN_CTRL (I4) register bits */ #define LX2G 0 /* Left Aux #2, LAUX2, Mix Gain*/ #define LX2G_SZ 5 /* LX2G field width */ #define LX2M 7 /* Left Aux #2 Mute */ /* IREG_RIGHT_AUX2_IN_CTRL (I5) register bits */ #define RX2G LX2G /* Right Aux #2, RAUX2, Mix Gn */ #define RX2G_SZ LX2G_SZ /* RX2G field width */ #define RX2M LX2M /* Right Aux #2 Mute */ /* IREG_LEFT_DAC_OUT_CTRL (I6) register bits */ #define LDA 0 /* Left DAC Attenuator */ #define LDA_SZ 5 /* LDA field width */ #define LDM 7 /* Left DAC mute */ /* IREG_RIGHT_DAC_OUT_CTRL (I7) register bits */ #define RDA LDA /* Right DAC Attenuator */ #define RDA_SZ LDA_SZ /* RDA field width */ #define RDM LDM /* Right DAC mute */ /* IREG_FS_PBACK_DATA_FMT (I8) register bits */ #define C2SL 0 /* Clock 2 Source select */ #define CFS 1 /* Clock Frequency divide sel */ #define CFS_SZ 3 /* CFS field width */ #define S_M 4 /* Stereo-Mono select */ #define C_L 5 /* Companded/Linear- select */ #define FMT 6 /* Audio data Format */ #define C_L_FMT_SZ 3 /* C_L and FMT fields combined */ /* IREG_INTFC_CONFIG (I9) register bits */ #define PEN 0 /* Playback Enable */ #define CEN 1 /* Capture Enable */ #define SDC 2 /* Single DMA Channel */ #define CAL 3 /* Calibration mode */ #define CAL_SZ 2 /* Calibration field width */ #define PPIO 6 /* Playback PIO enable */ #define CPIO 7 /* Capture PIO enable */ /* IREG_PIN_CTRL (I10) register bits */ #define IEN 1 /* Interrupt Enable */ #define DEN 3 /* Dither Enable */ #define XCTL0 6 /* XCTL Control */ #define XCTL1 7 /* XCTL Control */ /* IREG_ERR_STATUS_INIT (I11) register bits */ #define ORL 0 /* Overrange Left Defect */ #define ORL_SZ 2 /* ORL field width */ #define ORR 2 /* Overrange Right Defect */ #define ORR_SZ 2 /* ORR field width */ #define DRS 4 /* DRQ status */ #define ACI 5 /* Auto Calibrate in Progress */ #define PUR 6 /* Playback Underrun */ #define COR 7 /* Capture Overrun */ /* IREG_MODE_ID (I12) register bits */ #define ID 0 /* Codec ID */ #define ID_SZ 4 /* ID field width */ #define MODE2 6 /* MODE2 :enables expanded mode*/ /* IREG_LBACK_CTRL (I13) register bits */ #define LBE 0 /* Loopback Enable */ #define LBA 1 /* Loopback attenuation */ #define LBA_SZ 6 /* LBA field width */ /* IREG_ALT_FEATURE_EN1 (I16) register bits */ #define DACZ 0 /* DAC Zero */ #define SPE 1 /* Serial Port Enable */ #define SF 2 /* Serial Format */ #define SF_SZ 2 /* SF field width */ #define PMCE 4 /* Playback Mode Change Enable */ #define CMCE 5 /* Caputure Mode Change Enable */ #define TE 6 /* Timer Enable */ #define OLB 7 /* Output Level Bit */ /* IREG_ALT_FEATURE_EN2 (I17) register bits */ #define HPF 0 /* High Pass Filter- 1 enables */ #define XTALE 1 /* Crystal Enable */ #define APAR 2 /* ADPCM Playback acc reset */ #define TEST 4 /* Factory Test */ #define TEST_SZ 4 /* TEST field width */ /* IREG_LEFT_LINE_IN_CTRL (I18) register bits */ #define LLG 0 /* Left Line Mix Gain */ #define LLG_SZ 5 /* LLG field width */ #define LLM 7 /* Left Line Mute */ /* IREG_RIGHT_LINE_IN_CTRL (I19) register bits */ #define RLG LLG /* Right Line Mix Gain */ #define RLG_SZ LLG_SZ /* RLG field width */ #define RLM LLM /* Right Line Mute */ /* IREG_ALT_FEATURE_EN3 (I23) register bits */ #define ACF 0 /* ADPCM Capture and Freeze */ /* IREG_ALT_FEATURE_STAT (I24) register bits */ #define PU 0 /* Playback Underrun */ #define PO 1 /* Playback Overrun */ #define CO 2 /* Capture Overrun */ #define CU 3 /* Capture Underrun */ #define PINT 4 /* Playback Interrupt */ #define CINT 5 /* Capture Interrupt */ #define TINT 6 /* Timer Interrupt */ /* IREG_VER_CHIPID (I25) register bits */ #define VER 5 /* Version number */ #define VER_SZ 3 /* VER field width */ #define CID 0 /* Chip Identification */ #define CID_SZ 3 /* CID field size */ /* IREG_MONO_IO_CTRL (I26) register bits */ #define MIA 0 /* Mono Input Attenuation */ #define MIA_SZ 4 /* MIA field width */ #define MBY 5 /* Mono Bypass */ #define MOM 6 /* Mono output mute */ #define MIM 7 /* Mono input mute */ /* IREG_CAPTURE_DATA_FMT (I28) register bits */ #define CS_M 0 /* Capture Stereo-Mono select */ #define DEFAULT_INTFC_CONFIG 0xC3 #define DEFAULT_SAMPLE_RATE 44100 /* in Hz */ #define DEFAULT_ALT_FEATURE_EN1 0x8A #define XTAL1_TIMER_PERIOD 9.969 #define XTAL2_TIMER_PERIOD 9.92 /* Macro Functions */ #define SELECT_IREG(reg_index,ireg) \ ( *((volatile unsigned char *)(reg_index)) = \ *((volatile unsigned char *)(reg_index)) & \ (~(MASK_FIELD(IA,IA_SZ))) | (ireg) ) #endif