/**************************************************************************/
/*  DNA PROPRIETARY INFORMATION                                           */
/*  (C) Copyright 1998 by DNA Enterprises                                 */
/*  All rights reserved                                                   */
/**************************************************************************/

#ifndef _FMIC_H_
#define _FMIC_H_

#include "mt90810.h"

/*------------------------------------------------------------------------*/
/* General Definitions                                                    */
/*------------------------------------------------------------------------*/
/*
  These FMIC_x_BASEs need to be updated once the McEVM board is done.
*/
#ifdef _LITTLE_ENDIAN
#define FMIC_MOTHER_BASE0   0x01340000 
#define FMIC_MOTHER_BASE1   0x01740000
#else /* _BIG_ENDIAN */
#define FMIC_MOTHER_BASE0   0x01340003
#define FMIC_MOTHER_BASE1   0x01740003
#endif


#define FMIC_MAX_DEV       2


/*------------------------------------------------------------------------*/
/* MVIP FMIC Interface Definitions                                        */
/*------------------------------------------------------------------------*/
typedef enum
{
  FMIC_CLOSE = 0,
  FMIC_OPEN,
  FMIC_INITIALIZED
}
fmic_state;


typedef struct
{
  fmic_state state; 
  u32 base_addr;
}
FMIC_DEV;


typedef FMIC_DEV * FMIC_DEV_T;


#define FMIC_JUMER_1_2_SHORTED  1


/*------------------------------------------------------------------------*/
/* FMIC Timing Mode                                                       */
/*------------------------------------------------------------------------*/
typedef enum
{                             /* J1/J2   PLL_MODE MVIP_MST XCLK_SEL */
  FMIC_MVIP_BUS_TIMING = 0,   /* Shorted M=4,D=4  M=0,D=0  M=D=0    */
                              /* Open    M=4,D=6  M=0,D=1  M=D=0    */

  FMIC_MOTHER_BD_FREE_RUN,    /* Shorted M=0,D=4  M=1,D=0  M=D=0    */
                              /* Open    M=0,D=6  M=1,D=1  M=D=0    */

  FMIC_DAUGHTER_BD_FREE_RUN,  /* Shorted M=4,D=0  M=0,D=1  M=D=0    */
                              /* Open    M=6,D=0  M=1,D=1  M=D=0    */

  FMIC_MOTHER_BD_RCV_TIMING,  /* Shorted M=0,D=4  M=1,D=0  M=D=0    */
                              /* Open    M=0,D=6  M=1,D=1  M=D=0    */

  FMIC_DAUGHTER_BD_RCV_TIMING /* Shorted M=4,D=0  M=0,D=1  M=D=0    */
                              /* Open    M=6,D=0  M=1,D=1  M=D=0    */
}
fmic_timing_mode;



/*------------------------------------------------------------------------*/
/* FMIC DSi/DSo channel pair direction                                    */
/*------------------------------------------------------------------------*/
typedef enum
{
  FMIC_DSo_IN = 0,
  FMIC_DSi_IN
}
fmic_mvip_direction;


/*------------------------------------------------------------------------*/
/* Register ID                                                            */
/*------------------------------------------------------------------------*/
/*
31                               15                            0 bit
 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
   d                  m m         |                             |
                                  |                             |
                                  -------------------------------
                                             address

d - 0 = direct address, 1 = indirect address
mm - memory space selection for indirect address

To form a register ID:
----------------------
register_id = fmic_register_id | address;
*/ 

#define FMIC_MEM_SPACE_OFFSET   16
#define FMIC_ADDRESS(reg_id)    ((reg_id) & 0x0000FFFF)
#define FMIC_MEM_SPACE(reg_id)  \
        (((reg_id) >> FMIC_MEM_SPACE_OFFSET) & 0x000000FF)


#define FMIC_DIRECT_ADDR_ID   0x00000000
#define FMIC_INDIRECT_ADDR_ID 0x40000000


typedef enum
{
  /* Master Control/Status Register */
  FMIC_MASTER_REG_ID = 0x00000000,

  /* FMIC Control Registers */
  FMIC_CNTRL_REG_ID =
  (((u32)FMIC_CNTRL_REG) << FMIC_MEM_SPACE_OFFSET) | FMIC_INDIRECT_ADDR_ID,

  /* Data Memory */
  FMIC_DATA_MEMORY_ID = 
  (((u32)FMIC_DATA_MEMORY) << FMIC_MEM_SPACE_OFFSET) | FMIC_INDIRECT_ADDR_ID,

  /* Connection Memory Low Byte */
  FMIC_CONN_MEM_LOW_ID = 
  (((u32)FMIC_CONN_MEM_LOW) << FMIC_MEM_SPACE_OFFSET) | FMIC_INDIRECT_ADDR_ID,

  /* Connection Memory High Byte */
  FMIC_CONN_MEM_HIGH_ID =
  (((u32)FMIC_CONN_MEM_HIGH) << FMIC_MEM_SPACE_OFFSET) | FMIC_INDIRECT_ADDR_ID
}
fmic_register_id;


#ifndef _WINDOWS
/*-------------------------------------------------------------------------*/
/* Function Prototypes                                                     */
/*-------------------------------------------------------------------------*/
FMIC_DEV_T fmic_open(u32 fmic_base_addr);
int fmic_close(FMIC_DEV_T fmic_dev);
u32 fmic_read(FMIC_DEV_T fmic_dev, 
              u32 register_id);
int fmic_write(FMIC_DEV_T fmic_dev, 
               u32 register_id, 
               u32 value, 
               u32 mask);
int fmic_configure(FMIC_DEV_T fmic_dev, 
                   u32 fmic_configuration[][3]);

int fmic_init(FMIC_DEV_T fmic_dev, 
              fmic_timing_mode timing_mode);
int fmic_timing(FMIC_DEV_T fmic_dev, 
                fmic_timing_mode timing_mode);
int fmic_connect(FMIC_DEV_T fmic_dev, 
                 u32 out_chan, 
                 u32 in_chan);
int fmic_clear_connections(FMIC_DEV_T fmic_dev);
int fmic_direction(FMIC_DEV_T fmic_dev, 
                   u32 channel, 
                   fmic_mvip_direction direction);
int fmic_output_control(FMIC_DEV_T fmic_dev, 
                        u32 channel, 
                        int enable);
#endif

#endif