/******************************************************************************/ /* DNA PROPRIETARY INFORMATION */ /* (C) Copyright 1997,1998 by DNA Enterprises, Inc. */ /* All rights reserved */ /******************************************************************************/ /* MCBSP_DRV.H - Multichannel Serial Port driver routines header file. */ /* */ /* This module is the device driver for the multichannel buffered serial */ /* ports on the C6x. */ /* */ /* MACRO FUNCTIONS: */ /* */ /* FUNCTIONS: */ /* mcbsp_drv_init() - Init Multi-channel Buffered Serial Port driver */ /* mcbsp_open() - Open indicated McBSP for subsequent calls */ /* mcbsp_close() - Releases port for use by another routine/thread*/ /* mcbsp_config() - Configures MCBSP for operation. */ /* mcbsp_mc_config() - Configures multichannel selection */ /* mcbsp_reset() - Reset MCBSP. */ /* mcbsp_stop() - Stop tx, rx, sample rate and frame sync gens */ /* mcbsp_sync_receive() - Receive a buffer of data,CPU polled & blocking */ /* mcbsp_async_receive() - Receive a buffer of data, DMA and interrupt */ /* mcbsp_sync_send() - Xmit a buffer of data, CPU polled & blocking */ /* mcbsp_async_send() - Xmit a buffer of data, DMA and interrupt driven*/ /* mcbsp_cont_async_send - Continuously Xmit single or ping pong buffer */ /* */ /* REVISION HISTORY: */ /* */ /* DATE DESCRIPTION */ /* ------- ---------------------------------------------------------- */ /* 16JUL98 Added dma_esize to the Mcbsp_dma structure to support */ /* variable DMA element transfer sizes */ /* */ /******************************************************************************/ #ifndef _MCBSPDRV_H_ #define _MCBSPDRV_H_ #include #include /*----------------------------------------------------------------------------*/ /* DEFINES */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* MACRO DEFINITIONS */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* TYPEDEFS */ /*----------------------------------------------------------------------------*/ typedef struct Ping_pong_buff_struct { unsigned char *p_ping_buff; unsigned char *p_pong_buff; unsigned int num_bytes_ping; unsigned int num_bytes_pong; unsigned int ping_pong_flag; } Ping_pong_buffs; typedef struct Mcbsp_dma_struct { int continuous; unsigned char dma_esize; Dma_channel_idx dma_channel_idx; Dma_gidx_idx dma_gidx_idx; Dma_gadr_idx dma_gadr_idx; Dma_gcnt_idx dma_gcnt_idx; } Mcbsp_dma; typedef struct Mcbsp_handle_struct { int port; /* port number, 0 or 1,2 */ int state; /* OPEN, BUSY, CLOSED */ Ping_pong_buffs tx; /* transmit ping-pong buffers */ Ping_pong_buffs rx; /* receive ping-pong buffers */ Mcbsp_dma tx_dma; /* dma resources for transmit */ Mcbsp_dma rx_dma; /* dma resources for receive */ } Mcbsp_handle; typedef Mcbsp_handle * Mcbsp_dev; /* function typedefs for read and write callback functions */ typedef void Callback(Mcbsp_dev dev, int status ); typedef struct Mcbsp_tx_config_struct { unsigned char update; /* Update Tx Parameters? T/F */ unsigned char interrupt_mode; /* SPCR(2):XRDY,Blk,Frame,SyncErr */ unsigned char clock_polarity; /* PCR(1): Rise or Fall of CLKX */ unsigned char frame_sync_polarity; /* PCR(1): Active High or Low */ unsigned char clock_mode; /* PCR(1): External or Internal */ unsigned char frame_sync_mode; /* PCR(1): External or Internal */ unsigned char phase_mode; /* XCR(1): Single or Dual */ unsigned char frame_length1; /* XCR(7): 1 to 128 wpf for phase 1*/ unsigned char frame_length2; /* XCR(7): " " phase 2*/ unsigned char word_length1; /* XCR(3): bits per phase 1 word */ unsigned char word_length2; /* XCR(3): bits per phase 2 word */ unsigned char companding; /* XCR(2): ALAW ULAW or MSB or LSB */ unsigned char frame_ignore; /* XCR(1): T/F */ unsigned char data_delay; /* XCR(3): 0-2 Tx data delay */ unsigned char dummy[2]; /* pad bytes to 32 bit align */ } Mcbsp_tx_config; typedef struct Mcbsp_rx_config_struct { unsigned char update; /* Update Rx Parameters? T/F */ unsigned char interrupt_mode; /* SPCR(2): RRDY,Blk,Frame,Syncerr */ unsigned char justification; /* SPCR(2): RJZF, RJSE or LJZF */ unsigned char clock_polarity; /* PCR(1): Rise or Fall of CLKX */ unsigned char frame_sync_polarity; /* PCR(1): Active High or Low */ unsigned char clock_mode; /* PCR(1): External or Internal */ unsigned char frame_sync_mode; /* PCR(1): External or Internal */ unsigned char phase_mode; /* XCR(1): Single or Dual */ unsigned char frame_length1; /* XCR(7):1 to 128 wpf for phase 1 */ unsigned char frame_length2; /* XCR(7): " " phase 2*/ unsigned char word_length1; /* XCR(3): bits per phase 1 word */ unsigned char word_length2; /* XCR(3): bits per phase 2 word */ unsigned char companding; /* XCR(2): ALAW ULAW or MSB or LSB */ unsigned char frame_ignore; /* XCR(1): T/F */ unsigned char data_delay; /* XCR(3): 0-2 Rx data delay */ unsigned char dummy; /* pad bytes */ } Mcbsp_rx_config; typedef struct Mcbsp_srg_config_struct { unsigned char update; /* Update SRGR Parameters? T/F */ unsigned char clock_sync; /* SRGR(1):GSYNC_OFF or GSYNC_ON */ unsigned char clks_polarity; /* SRGR(1):rising or falling edge */ unsigned char clks_mode; /* SRGR(1):external or internal */ unsigned char frame_sync_mode; /* SRGR(1):FSX due to DXR-XSR, FSG */ unsigned short frame_period; /* SRGR(12): Frame period 1-4096 */ unsigned char frame_width; /* SRGR(8): 1 to 256 CLKG periods */ unsigned char clock_divider; /* SRGR(8): SRGR clock dvdr: 1-256 */ } Mcbsp_srg_config; typedef struct Mcbsp_config_struct { unsigned int loopback; /* SPCR(1): TRUE or FALSE */ Mcbsp_tx_config tx; Mcbsp_rx_config rx; Mcbsp_srg_config srg; } Mcbsp_config; typedef struct Mcbsp_mc_config_struct { unsigned char rx_mc_sel_en; /* MCCR(1): TRUE or FALSE */ unsigned char rx_blockA; /* MCCR(2): rx block 1,3,5 or 7 sel */ unsigned char rx_blockB; /* MCCR(2): rx block 0,2,4 or 6 sel */ unsigned char dummy1; /* pad bytes to 32 bit align */ unsigned short rx_blockA_ch_en; /* RCER(16): 16 chan enable bitmask */ unsigned short rx_blockB_ch_en; /* RCER(16): 16 chan enable bitmask */ unsigned char tx_mc_sel_en; /* MCCR(2): enable, masking modes */ unsigned char tx_blockA; /* MCCR(2): tx block 1,3,5 or 7 sel */ unsigned char tx_blockB; /* MCCR(2): tx block 0,2,4 or 6 sel */ unsigned char dummy2; /* pad bytes to 32 bit align */ unsigned short tx_blockA_ch_en; /* XCER(16): 16 chan enable bitmask */ unsigned short tx_blockB_ch_en; /* XCER(16): 16 chan enable bitmask */ } Mcbsp_mc_config; /*-----------------------------------------------------------------------------*/ /* FUNCTION DECLARATIONS */ /*-----------------------------------------------------------------------------*/ /******************************************************************************/ /* MCBSP_DRV_INIT - Initialize MCBSP driver for use. */ /* */ /* This function is responsible for initializing the MCBSP driver. Memory */ /* is allocated for the MCBSP handle structures This */ /* function must be called once before any other MCBSP calls. */ /* */ /******************************************************************************/ int mcbsp_drv_init(void); /* RET: OK or ERROR if mallocs fail */ /******************************************************************************/ /* MCBSP_OPEN - Open a MCBSP port for use. */ /* */ /* This function opens the indicated port by returning a pointer to the */ /* MCBSP_HANDLE used for subsequent McBSP operations. */ /* */ /******************************************************************************/ Mcbsp_dev mcbsp_open( /*RET: initialized Mcbsp_dev or NULL */ int port /*IN: port number (0 or 1) to open */ ); /******************************************************************************/ /* MCBSP_CLOSE - Flag MCBSP port as CLOSED. */ /******************************************************************************/ void mcbsp_close(Mcbsp_dev dev /* IN: open device handle to close */ ); /******************************************************************************/ /* MCBSP_CONFIG - Configure a MCBSP port. */ /* */ /* This function performs configuration by writing to applicable fields */ /* within the SPCR, PCR, RCR, XCR and SRGR. The MCCR (Multi-channel */ /* Control Register) is configured by the mcbsp_mc_config() routine. */ /* Note: MCBSP config will take the indicated sections out of operation */ /* by clearing X/RRST to 0 for the receiver and transmitter, */ /* respectively. */ /* */ /******************************************************************************/ int mcbsp_config( /* RET: OK or ERROR */ Mcbsp_dev dev, /* IN:MCBSP handle */ Mcbsp_config *p_mcbsp_config /* IN:MCBSP configuration dat */ ); /******************************************************************************/ /* MCBSP_MC_CONFIG - Configure multi-channel selection operation */ /* */ /* This function performs multi-channel selection configuration by */ /* writing to the applicable fields in MCCR, RCER, and XCER. */ /* */ /******************************************************************************/ int mcbsp_mc_config( /* RET: OK or ERROR */ Mcbsp_dev dev, /* IN:MCBSP handle */ Mcbsp_mc_config *p_mcbsp_mc_config /* IN:MCBSP mc config data */ ); /*****************************************************************************/ /* MCBSP_RESET - Resets all McBSP registers to their POR values */ /* */ /* This routine will reset all McBSP memory mapped registers to their */ /* Power On Reset (POR) values. */ /*****************************************************************************/ void mcbsp_reset(Mcbsp_dev dev); /*****************************************************************************/ /* MCBSP_STOP - Stop tx, rx, sample rate & frame sync generators */ /* */ /* This routine will place the transmit, receive and sample rate */ /* generator of the selected MCBSP port into reset (disabled) state. */ /*****************************************************************************/ void mcbsp_stop(Mcbsp_dev dev); /******************************************************************************/ /* MCBSP_SYNC_RECEIVE- Rx a buffer of data from MCBSP,blocking until complete*/ /* */ /* This routine performs a simple blocking CPU read from the DRR register */ /* of the selected MCBSP port. This function does not return until */ /* num_bytes of data have been transferred to *p_buffer. Note that the */ /* argument num_bytes refers to the number of bytes transferred to */ /* p_buffer rather than the number of words read from DRR. Argument */ /* pack_data may be set to TRUE so that the minimum number of bytes will */ /* be used to represent the data words read. The pack_data argument is */ /* only applicable in single phase transfers, and will cause this function*/ /* to return ERROR if TRUE and the port is configured for multiphase. */ /* */ /******************************************************************************/ int mcbsp_sync_receive( Mcbsp_dev dev, unsigned char *p_buffer, unsigned int num_bytes, unsigned int frame_sync_enable, Mcbsp_dev frame_sync_dev, int pack_data ); /******************************************************************************/ /* MCBSP_ASYNC_RECEIVE - Asynchronous Receive on MCBSP */ /* */ /* This function sets up a DMA transfer and enables the DMA block complete*/ /* interrupt whose ISR calls the indicated read callback function. */ /******************************************************************************/ int mcbsp_async_receive( Mcbsp_dev dev, unsigned char *p_buffer, unsigned int num_bytes, unsigned int frame_sync_enable, Mcbsp_dev frame_sync_dev, Callback *p_ract ); /******************************************************************************/ /* MCBSP_SYNC_SEND - Writes a buffer of data from MCBSP */ /* */ /* This routine performs a simple blocking CPU write to the DXR register */ /* of the selected MCBSP port. This function does not return until */ /* num_bytes of data have been transmitted from p_buffer. Note that the */ /* argument num_bytes refers to the number of bytes to be transmitted */ /* rather than the number of words written to DXR. Argument */ /* packed_data may be set to TRUE to indicate that only the significant */ /* bytes of each word to be transmitted reside in p_buffer. The size of */ /* the data words is determined from WDLEN1 in SPCR. Multiphase packed */ /* transmits are currently not supported. If the selected transmitter has*/ /* been configured for multiphase mode and packed_data is TRUE, this */ /* function will return ERROR status. */ /* */ /******************************************************************************/ int mcbsp_sync_send( Mcbsp_dev dev, unsigned char *p_buffer, unsigned int num_bytes, unsigned int frame_sync_enable, Mcbsp_dev frame_sync_dev, int packed_data); /******************************************************************************/ /* MCBSP_ASYNC_SEND - Asynchronous DMA driven send with ISR call to Write */ /* callback function. */ /* */ /******************************************************************************/ int mcbsp_async_send( Mcbsp_dev dev, unsigned char *p_buffer, unsigned int num_bytes, unsigned int frame_sync_enable, Mcbsp_dev frame_sync_dev, Callback *p_wact ); /******************************************************************************/ /* MCBSP_CONT_ASYNC_SEND - Asynchronous DMA driven continuous send with ISR */ /* call to callback function. */ /* */ /* This routine extends the functionality of the mcbsp_async_send() by */ /* providing continuous mode operation via the autoinitialization capability */ /* of the DMA controller. Both continuous (ping-pong) operation and */ /* repetitive (replay) operation is supported. */ /* */ /******************************************************************************/ int mcbsp_cont_async_send( Mcbsp_dev dev, unsigned char *p_ping_buff, unsigned char *p_pong_buff, unsigned int num_bytes, unsigned int frame_sync_enable, Mcbsp_dev frame_sync_dev, Callback *p_wact ); /******************************************************************************/ /* MCBSP_CONT_ASYNC_RECEIVE - Asynchronous DMA driven continuous receive */ /* with ISR call to callback function. */ /* */ /* This routine extends the functionality of the mcbsp_async_recieve() by */ /* providing continuous mode operation via the autoinitialization capability */ /* of the DMA controller. Both continuous (ping-pong) operation and */ /* repetitive (replay) operation is supported. */ /* */ /******************************************************************************/ int mcbsp_cont_async_receive( Mcbsp_dev dev, unsigned char *p_ping_buff, unsigned char *p_pong_buff, unsigned int num_bytes, unsigned int frame_sync_enable, Mcbsp_dev frame_sync_dev, Callback *p_wact ); /******************************************************************************/ /* MCBSP_DMA_ESIZE_CONFIG - Configure DMA element transfer size */ /* */ /* This routine allows the element size of DMA transfers to be reconfigured */ /* to 8, 16, or 32 bits. Valid values are DMA_ESIZE8, DMA_ESIZE16 and */ /* DMA_ESIZE32. All subsequent calls to mcbsp_async_receive(), */ /* mcbsp_async_send(), and mcbsp_cont_async_send() will operate with the */ /* defined element size. */ /******************************************************************************/ static void mcbsp_dma_esize_config( Mcbsp_dev dev, unsigned char esize ); #endif /* _MCBSP_DRV_H_ */