/**************************************************************************/ /* DNA PROPRIETARY INFORMATION */ /* (C) Copyright 1998 by DNA Enterprises */ /* All rights reserved */ /**************************************************************************/ #ifndef _MT90810_H_ #define _MT90810_H_ /*------------------------------------------------------------------------*/ /* General Definitions */ /*------------------------------------------------------------------------*/ #ifndef LITERAL_TYPEDEF #define LITERAL_TYPEDEF typedef unsigned char u8; typedef unsigned short u16; typedef unsigned int u32; typedef unsigned long u40; #endif #ifndef REG8 #define REG8(addr) (*(volatile u8 *)(addr)) #endif /*------------------------------------------------------------------------*/ /* MVIP FMIC General Definitions */ /*------------------------------------------------------------------------*/ #define FMIC_MAX_CHANNEL 384 /* 1 base */ #define FMIC_CHAN_START 0 /* 0 base */ #define FMIC_CHAN_END 255 /* 0 base */ #define FMIC_LOCAL_CHAN_START 256 /* 0 base */ #define FMIC_LOCAL_CHAN_END 383 /* 0 base */ #define FMIC_LAST_CHAN 383 /* 0 base */ #define FMIC_MAX_DS_CHANNEL 32 /* 1 base */ #define FMIC_MAX_STREAM 8 /* 1 base */ /*------------------------------------------------------------------------*/ /* Registers */ /*------------------------------------------------------------------------*/ #define FMIC_MR 0x00 /* Master Control/Status Reg */ #define FMIC_LAR 0x04 /* Low Address Register */ #define FMIC_AMR 0x08 /* Address Mode Register */ #define FMIC_IDR 0x0C /* Indirect Data Register */ /*------------------------------------------------------------------------*/ /* Master Control/Status Register */ /*------------------------------------------------------------------------*/ typedef enum { FMIC_PLL_UNLCK = 0x80, FMIC_DMAW_OV = 0x40, FMIC_DMAR_OV = 0x20, FMIC_CLK_ERR = 0x10, FMIC_MVIP_MST = 0x08, FMIC_DMA_EN = 0x04, FMIC_EN = 0x02, FMIC_RESET = 0x01 } fmic_master_reg; /*------------------------------------------------------------------------*/ /* Address Mode Register */ /*------------------------------------------------------------------------*/ /* Auto increment/decrement mode */ #define FMIC_NO_AUTO 0x00 /* Normal Mode */ #define FMIC_AUTO_R 0x40 /* Auto increment after read of IDR */ #define FMIC_AUTO_W 0x80 /* Auto increment after write of IDR */ #define FMIC_AUTO_WR 0xC0 /* Auto increment after read or write of IDR */ /* Selects the memory space */ #define FMIC_CNTRL_REG 0x00 /* FMIC Control Registers */ #define FMIC_DATA_MEMORY 0x10 /* Data Memory */ #define FMIC_CONN_MEM_LOW 0x20 /* Connection Memory Low Byte */ #define FMIC_CONN_MEM_HIGH 0x30 /* Connection Memory High Byte */ /*------------------------------------------------------------------------*/ /* FMIC Control Register (read/write) */ /*------------------------------------------------------------------------*/ /* Indirect Address */ typedef enum { FMIC_CLK_CNTRL = 0, /* Clock Control Register */ FMIC_LOC_CLK = 1, /* Local Output Clock Control */ FMIC_SER_MODE = 2, /* Local Serial Configuration Register */ FMIC_FRMA_STRT = 4, /* Frame Group A start register */ FMIC_FRMA_MODE = 5, /* Frame Group A mode register */ FMIC_FRMB_STRT = 6, /* Frame Group B start register */ FMIC_FRMB_MODE = 7, /* Frame Group B mode register */ FMIC_DIAG_REG = 12 /* Chip diagnostic bits */ } fmic_indirect_addr; /*------------------------------------------------------------------------*/ /* Clock Control Register */ /*------------------------------------------------------------------------*/ #define FMIC_SEL_S8K_MASK 0xC0 #define FMIC_PLL_MODE_MASK 0x1C #define FMIC_XCLK_SEL_MASK 0x03 /* SEL_S8K */ typedef enum { FMIC_EX_8KA = 0x00, /* Select EX_8KA as SEC8K output */ FMIC_EX_8KB = 0x40, /* Select EX_8KB as SEC8K output */ FMIC_FRAME = 0x80 /* Select FRAME as SEC8K output */ } fmic_sel_s8k; /* EN_SEC8K */ #define FMIC_EN_SEC8K 0x20 /* Enables SEC8K as output */ /* PLL_MODE */ typedef enum { FMIC_PLL_MODE_0 = 0x00, /* FMIC as Timing Master */ FMIC_PLL_MODE_1 = 0x04, /* SEC8K, FMIC as MVIP Master /w no frame sync */ FMIC_PLL_MODE_2 = 0x08, /* EX8KA, FMIC as MVIP Master /w no frame sync */ FMIC_PLL_MODE_3 = 0x0C, /* EX8KB, FMIC as MVIP Master /w no frame sync */ FMIC_PLL_MODE_4 = 0x10, /* FMIC as MVIP Slave */ FMIC_PLL_MODE_5 = 0x14, /* SEC8K, FMIC as MVIP Master /w frame sync */ FMIC_PLL_MODE_6 = 0x18, /* EX8KA, FMIC as MVIP Master /w frame sync */ FMIC_PLL_MODE_7 = 0x1C /* EX8KB, FMIC as MVIP Master /w frame sync */ } fmic_pll_mode; /* XCLK_SEL */ typedef enum { FMIC_XCLK_16MHZ = 0x00, /* 16.384 MHz */ FMIC_XCLK_8MHZ = 0x01, /* 8.192 MHz */ FMIC_XCLK_4MHZ = 0x02 /* 4.096 MHz */ } fmic_xclk_sel; /*-------------------------------------------------------------------------*/ /* Local Output Clock Control Register */ /*-------------------------------------------------------------------------*/ typedef enum { FMIC_DACK1 = 0x80, /* Read-only, logic value of /DACK1 pin */ FMIC_DACK0 = 0x40, /* Read-only, logic value of /DACK0 pin */ FMIC_EX8KB = 0x20, /* Read-only, logic value of EX8KB pin */ FMIC_EX8KA = 0x10, /* Read-only, logic value of EX8KA pin */ FMIC_INV_CLK8 = 0x08, /* When set, inverts 8.192MHz CLK8 output pin */ FMIC_INV_CLK4 = 0x04, /* When set, inverts 4.096MHz CLK4 output pin */ FMIC_INV_CLK2 = 0x02, /* When set, inverts 2.048MHz CLK2 output pin */ FMIC_INV_FRM = 0x01 /* When set, inverts FRAME output signal */ } fmic_local_clock; /*-------------------------------------------------------------------------*/ /* Local Serial Configuration Register */ /*-------------------------------------------------------------------------*/ typedef enum { FMIC_2MHZ_STREAMS = 0x00, /* 2MHz streams */ FMIC_4MHZ_STREAMS = 0x01, /* 4MHz streams */ FMIC_8MHZ_STREAMS = 0x02, /* 8MHz streams */ FMIC_SPLIT_2MHZ_4MHZ_STREAMS = 0x03 /* Split 2MHz/4MHz streams */ } fmic_serial_mode; /*-------------------------------------------------------------------------*/ /* Framing Registers */ /*-------------------------------------------------------------------------*/ #define FMIC_FRAME_MODE_MASK 0xC0 #define FMIC_FRAME_TYPE_MASK 0x20 #define FMIC_FRAME_BIT_RATE_MASK 0x18 typedef enum { FMIC_FRAME_A = 0, /* group A */ FMIC_FRAME_B /* group B */ } fmic_frame_group; typedef enum { FMIC_FRAME_MODE0 = 0x00, /* Programmed output */ FMIC_FRAME_MODE1 = 0x40, /* DSi/DSo output enables */ FMIC_FRAME_MODE2 = 0x80, /* Normal Framing */ FMIC_FRAME_MODE3 = 0xC0 /* Inverted Framing */ } fmic_frame_mode; typedef enum { FMIC_ONE_BIT_WIDE = 0x00, /* Frame pulse is one bit cell wide */ FMIC_EIGHT_BIT_WIDE = 0x20 /* Frame pulse is eight bit cell wide */ } fmic_frame_type; typedef enum { FMIC_2MBS_BIT_RATE = 0x00, /* 2Mb/s data rate */ FMIC_4MBS_BIT_RATE = 0x08, /* 4Mb/s data rate */ FMIC_8MBS_BIT_RATE = 0x10 /* 8Mb/s data rate */ } fmic_bit_rate; /*-------------------------------------------------------------------------*/ /* Connection Memory */ /*-------------------------------------------------------------------------*/ typedef enum { /* Connection Memory High Bits for MVIP Channels */ FMIC_MVIP_DC = 0x08, FMIC_MVIP_MC = 0x04, FMIC_MVIP_OE = 0x02, FMIC_MVIP_CAB8 = 0x01, /* Connection Memory High Bits for Local Channels */ FMIC_LOCAL_CST = 0x08, FMIC_LOCAL_MC = FMIC_MVIP_MC, FMIC_LOCAL_CE = 0x02, FMIC_LOCAL_CAB8 = 0x01 } fmic_conn_mem_high; #ifndef _WINDOWS /*-------------------------------------------------------------------------*/ /* Function Prototypes */ /*-------------------------------------------------------------------------*/ void fmic_initialize(u32 base_addr); u8 fmic_idr_read(u32 base_addr, fmic_indirect_addr indirect_addr, u8 address_mode); void fmic_idr_write(u32 base_addr, fmic_indirect_addr indirect_addr, u8 address_mode, u8 value); int fmic_is_pll_unlock_asserted(u32 base_addr); int fmic_is_dmaw_ov_asserted(u32 base_addr); int fmic_is_dmar_ov_asserted(u32 base_addr); int fmic_is_clk_err_asserted(u32 base_addr); void fmic_set_mvip_bus_as_master(u32 base_addr); void fmic_set_mvip_bus_as_slave(u32 base_addr); void fmic_enable_dma(u32 base_addr); void fmic_disable_dma(u32 base_addr); void fmic_enable(u32 base_addr); void fmic_disable(u32 base_addr); void fmic_reset(u32 base_addr); u8 fmic_clock_control_read(u32 base_addr); void fmic_clock_control_write(u32 base_addr, u8 value); void fmic_select_ex_8ka(u32 base_addr); void fmic_select_ex_8kb(u32 base_addr); void fmic_select_frame(u32 base_addr); void fmic_select_8k_src(u32 base_addr, fmic_sel_s8k sel_s8k); void fmic_enable_sec8k(u32 base_addr); void fmic_disable_sec8k(u32 base_addr); void fmic_set_pll_mode0(u32 base_addr, fmic_xclk_sel xclk_sel); void fmic_set_pll_mode4(u32 base_addr); void fmic_set_pll_mode1(u32 base_addr); void fmic_set_pll_mode2(u32 base_addr); void fmic_set_pll_mode3(u32 base_addr); void fmic_set_pll_mode5(u32 base_addr); void fmic_set_pll_mode6(u32 base_addr); void fmic_set_pll_mode7(u32 base_addr); u8 fmic_local_clock_read(u32 base_addr); void fmic_local_clock_write(u32 base_addr, u8 value); int fmic_get_dack1_pin_value(u32 base_addr); int fmic_get_dack0_pin_value(u32 base_addr); int fmic_get_ex8kb_pin_value(u32 base_addr); int fmic_get_ex8ka_pin_value(u32 base_addr); void fmic_inverts_local_clock(u32 base_addr, fmic_local_clock clock); void fmic_uninverts_local_clock(u32 base_addr, fmic_local_clock clock); void fmic_set_local_serial_mode(u32 base_addr, fmic_serial_mode mode); void fmic_set_frame_mode(u32 base_addr, fmic_frame_group group, fmic_frame_mode mode); int fmic_set_frame_type(u32 base_addr, fmic_frame_group group, fmic_frame_type type); int fmic_set_frame_bit_rate(u32 base_addr, fmic_frame_group group, fmic_bit_rate rate); int fmic_set_frame_start(u32 base_addr, fmic_frame_group group, u32 start); void fmic_setup_conn_mode(u32 base_addr, u8 auto_mode, u8 memory_space, u32 initial_indirect_addr); void fmic_set_conn_mem_high(u32 base_addr, u32 output_chan, fmic_conn_mem_high mask); void fmic_clear_conn_mem_high(u32 base_addr, u32 output_chan, fmic_conn_mem_high mask); void fmic_init_conn_mem(u32 base_addr); void fmic_init_mvip_conn_mem(u32 base_addr); void fmic_init_local_conn_mem(u32 base_addr); void fmic_cross_connect(u32 base_addr, u32 output_chan, u32 input_chan); void fmic_disconnect(u32 base_addr, u32 output_chan, u32 idle_code); void fmic_write_conn_mem(u32 base_addr, u32 output_chan, u32 value); u8 fmic_read_conn_data(u32 base_addr, u32 input_chan); void fmic_set_chan_as_conn_mode(u32 base_addr, u32 output_chan); void fmic_set_chan_as_msg_mode(u32 base_addr, u32 output_chan); void fmic_set_mvip_dsi_as_input(u32 base_addr, u32 output_chan); void fmic_set_mvip_dso_as_input(u32 base_addr, u32 output_chan); void fmic_enable_mvip_output(u32 base_addr, u32 output_chan); void fmic_disable_mvip_output(u32 base_addr, u32 output_chan); void fmic_set_local_chan_cts_bit(u32 base_addr, u32 output_chan); void fmic_clear_local_chan_cts_bit(u32 base_addr, u32 output_chan); void fmic_enable_local_chan_dma(u32 base_addr, u32 output_chan); void fmic_disable_local_chan_dma(u32 base_addr, u32 output_chan); int fmic_is_local_channel(u32 channel); int fmic_is_mvip_bus_master(u32 base_addr); int fmic_is_dma_enable(u32 base_addr); int fmic_is_enable(u32 base_addr); #endif #endif