/**************************************************************************/
/*  DNA PROPRIETARY INFORMATION                                           */
/*  (C) Copyright 1998 by DNA Enterprises                                 */
/*  All rights reserved                                                   */
/**************************************************************************/

#ifndef _T1E1_H_
#define _T1E1_H_

#include "falc_lh.h"


/*------------------------------------------------------------------------*/
/* General Definitions                                                    */
/*------------------------------------------------------------------------*/
#define T1E1_MAX_DEV 2


/*------------------------------------------------------------------------*/
/* Interface Definitions                                                  */
/*------------------------------------------------------------------------*/
typedef enum
{
  T1E1_CLOSE = 0,
  T1E1_OPEN,
  T1E1_INITIALIZED
}
t1e1_state;


typedef enum
{
  T1E1_E1 = PCM_30_MODE,
  T1E1_T1 = PCM_24_MODE
}
t1e1_line_mode;


typedef enum
{
  T1E1_T1_AMI  = FALC_T1_AMI,
  T1E1_T1_B8ZS = FALC_T1_B8ZS,
  T1E1_E1_AMI  = FALC_E1_AMI,
  T1E1_E1_HDB3 = FALC_E1_HDB3
}
t1e1_line_code;


typedef enum
{
  T1E1_T1_D4              = FALC_F12,
  T1E1_T1_ESF             = FALC_ESF,
  T1E1_E1_DOUBLEFRAME     = FALC_DOUBLEFRAME,
  T1E1_E1_CRC4_MULTIFRAME = FALC_CRC4_MULTIFRAME
}
t1e1_framing_mode;


typedef enum
{                                   /* J1/ LIM0    LIM1  FMIC-   EN_FRM_L */
                                    /* J2  .MAS    .DCOC MSTR             */
  T1E1_MVIP_BUS_TIMING = 0,         /* S   M=1,D=1 M=D=1 M=1,D=1 M=1,D=1  */
                                    /* O   M=1,D=1 M=D=1 M=1,D=1 M=0,D=1  */

  T1E1_RCV_TIMING,                  /* S   M=0,D=0 M=D=1 M=x,D=x M=1,D=1  */
                                    /* O   M=0,D=0 M=D=1 M=x,D=x M=0,D=1  */

  T1E1_MOTHER_BD_FREE_RUN,          /* S   M=1,D=1 M=D=1 M=0,D=1 M=1,D=1  */
                                    /* O   M=1,D=1 M=D=1 M=0,D=1 M=0,D=1  */

  T1E1_DAUGHTER_BD_FREE_RUN,        /* S   M=1,D=1 M=D=1 M=1,D=0 M=1,D=1  */
                                    /* O   M=1,D=1 M=D=1 M=1,D=0 M=1,D=0  */

  T1E1_MOTHER_BD_RCV_TIMING,        /* S   M=0,D=0 M=D=1 M=x,D=x M=1,D=1  */
                                    /* O   M=0,D=0 M=D=1 M=x,D=x M=0,D=1  */

  T1E1_XMIT_MOTHER_BD_RCV_TIMING,   /* S   M=0,D=1 M=D=1 M=x,D=1 M=1,D=1  */
                                    /* O   M=0,D=1 M=D=1 M=x,D=1 M=0,D=1  */

  T1E1_XMIT_DAUGHTER_BD_RCV_TIMING, /* S   M=1,D=0 M=D=1 M=1,D=x M=1,D=1  */
                                    /* O   M=1,D=0 M=D=1 M=1,D=x M=1,D=0  */

  T1E1_DAUGHTER_BD_RCV_TIMING       /* S   M=0,D=0 M=D=1 M=x,D=x M=1,D=1  */
                                    /* O   M=0,D=0 M=D=1 M=x,D=x M=1,D=0  */
}
t1e1_sync_mode;


typedef enum
{
  T1E1_NO_LOOPBACK = 0,
  T1E1_LOCAL_LOOPBACK = LOCAL_LOOP_BACK,
  T1E1_PAYLOAD_LOOPBACK = PAYLOAD_LOOP_BACK,
  T1E1_REMOTE_LOOPBACK = REMOTE_LOOP_BACK,
  T1E1_CHANNEL_LOOPBACK = CHANNEL_LOOP_BACK,
  T1E1_LOCAL_REMOTE_LOOPBACK
}
t1e1_loopback_mode;


/*------------------------------------------------------------------------*/
/* T1/E1 Framer/LIU Interface Definitions                                 */
/*------------------------------------------------------------------------*/
typedef struct
{
  t1e1_state       state;
  u32              base_addr;
  FALC_DEVICE_CTRL falc;
}
T1E1_DEV;


typedef T1E1_DEV * T1E1_DEV_T;


#ifndef _WINDOWS
/*-------------------------------------------------------------------------*/
/* Function Prototypes                                                     */
/*-------------------------------------------------------------------------*/
T1E1_DEV_T t1e1_open(u32 t1e1_base_addr);
int t1e1_close(T1E1_DEV_T t1e1_dev);
int t1e1_install(T1E1_DEV_T t1e1_dev, 
                 u32 register_id, 
                 u32 mask,
                 T1E1_CALLBACK_T callback);
u32 t1e1_read(T1E1_DEV_T t1e1_dev,
              u32 register_id);
int t1e1_write(T1E1_DEV_T t1e1_dev,
               u32 register_id,
               u32 value,
               u32 mask);
int t1e1_configure(T1E1_DEV_T t1e1_dev,
                   u32 t1e1_configuration[][3]);

int t1e1_reset(T1E1_DEV_T t1e1_dev);
int t1e1_init(T1E1_DEV_T t1e1_dev,
              t1e1_line_mode line_mode, 
              t1e1_line_code line_code_mode,
              t1e1_framing_mode framing_mode,
              t1e1_sync_mode sync_mode,
              t1e1_loopback_mode loopback_mode);
int t1e1_linecode(T1E1_DEV_T t1e1_dev,
                  t1e1_line_code line_code);
int t1e1_framing(T1E1_DEV_T t1e1_dev,
                 t1e1_framing_mode framing_mode);
int t1e1_sync(T1E1_DEV_T t1e1_dev,
              t1e1_sync_mode sync_mode);
int t1e1_loopback(T1E1_DEV_T t1e1_dev,
                  t1e1_loopback_mode loopback_mode);
int t1e1_channel_loopback(T1E1_DEV_T t1e1_dev,
                          u32 channel, 
                          int loopback_enable,
                          u32 idle_code);
#endif

#endif