Instruction Set Architecture
Address 8/16/32 bit data + 64 bit data on C67x
Load-store RISC architecture with 2 data paths
- 16 32-bit registers per data path (A0-15 and B0-15)
- 48 instructions (C62x) and 79 instructions (C67x)
Two parallel data paths with 32-bit RISC units
- Data unit - 32-bit address calculations (modulo, linear)
- Multiplier unit - 16 bit x 16 bit with 32-bit result
- Logical unit - 40-bit (saturation) arithmetic & compares
- Shifter unit - 32-bit integer ALU and 40-bit shifter
- Conditionally executed based on registers A1-2 & B0-2
- Work with two 16-bit halfwords packed into 32 bits