TMS320C54x Pipeline
Six-stage pipeline
- Prefetch: load address of next instruction onto bus
- Fetch: get next instruction
- Decode: decode next instruction to determine type of memory access for operands
- Access: read operands address
- Read: read data operand(s)
- Execute: write data to bus
Instructions
- 1-3 words long (most are one word long)
- 1-6 cycles to execute (most take one cycle) not counting external (off-chip) memory access penalty