Proc. IEEE Asilomar Conference on Signals, Systems, and Computers, Oct. 30-Nov. 2, 2005.

Low-Power Multipliers with Data Wordlength Reduction

Kyungtae Han, Brian L. Evans and Earl E. Swartzlander, Jr.

Dept. of Electrical and Computer Enginereing, The University of Texas at Austin, Austin, TX 78712 USA - -

Slides - Paper - Software - Wordlength Reduction


Multiprecision multipliers reduce power consumption by selecting smaller multipliers(i.e., submultiplier) according to the wordsize of the input operands. However, arbitrary levels of bit precision are not achieved by multiprecision multipliers. We have proposed wordlength reduction techniques that reduce power consumption with arbitrary levels of bit precision. In this paper, the signed right shift method and the truncation method are applied to a 16-bit radix-4 modified Booth multiplier and a 16-bit Wallace multiplier. The truncation method with 8 bit operands reduces the power consumption by 56% in the Wallace multiplier and 31% in the Booth multiplier. The signed right shift method shows no power reduction in the Wallace multiplier and 25% power reduction in the Booth multiplier. Unequal levels of precision in operands show different power reduction value for the Booth multiplier. The non-recoded operand in the Booth multiplier with 8-bit reduction has 13% more sensitivity in power consumption than the recoded multiplicand.

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Last Updated 11/11/04.