Proc. IEEE Custom Integrated Circuits Conference, Sep. 15-17, 2014.

An All Digital PWM-Based Delta Sigma ADC with an Inherently Matched Multi-Bit Quantizer/DAC

Wooyoung Jung, Yousof Mortazavi, Brian L. Evans and Arjang Hassibi

Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712 USA - - -



An all-digital PWM-based delta-sigma ADC is proposed. This system takes advantages of the duration of a pulse, rather than voltage or current, as the analog operand used in its closed-loop operation. Unlike VCO-based ADCs, this ADC as a linear input sampling stage with adequate uncalibrated performance. Furthermore, the architecture allows inherently matched multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. A 3-bit prototype of this ADC in 0.18 um CMOS process is implemented, tested, and presented. With an OSR of 72 and a bandwidth of 1 MHz, it achieves a dynamic range of 51 dB and SNDR of 49.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm2.

The test and measurement setup was supported by an equipment donation from National Instruments. The analog-to-digital converter chip was fabricated by the Taiwan Semiconductor Manufacturing Company.

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Last Updated 09/11/14.