Do people use MIPS in VLIW architecture?

For the Texas Instruments TMS320C6000 family of VLIW DSPs, TI often quotes RISC MIPS. Why? Because the C6x has 8 parallel RISC processors. With a maximum throughput of 1 VLIW instruction per clock cylce, 8 RISC instructions can in theory be excuted each clock cycle. So, a 300 MHz C6x can execute a maximum of 2400 RISC MIPS. But, in practice, perhaps only half of the RISC processors are active in any one instruction because there is just not that much functional parallelism to take advantage of. For control code, two processors are typically active per VLIW instruction. For an FIR filter, an FFT, or IIR filter, all eight RISC processors are operating in parallel. (It takes four RISC processors to compute one filter tap.) A lot of code falls in between these two extremes.

Another measure is the number of multiply-accumulates (MACs). The C6x can perform two multiply-accumulates per clock cycle. So, a 300 MHz C6x can perform a maximum of 600 million MACs.

More realistic measures of processor performance is based on a set of benchmarks. The two leading independent benchmarking methodologies for embedded processors follow:

1. Berkeley Design Technology Inc.
   • Results: http://www.bdti.com/bdtimark/results.htm
   • White paper: http://www.bdti.com/articles/wtpaper.htm
   The higher the benchmark result, the faster the processor. The BDTI benchmark only measures speed for a set of 11 simple 1-D kernels (FIR filter, IIR filter, etc.).
2. EDN Embedded Microprocessor Benchmark Consortium
   This benchmark was developed by a consortium of companies. The benchmark includes kernels and applications. It is concentrated on embedded controls applications, but also addresses embedded 1-D signal processing applications.

http://www.ece.utexas.edu/~bevans/courses/realtime/lectures/25_DSPs/

Mail comments about this page to bevans@ece.utexas.edu.