This Report was presented to the Faculty of the Graduate School of the University of Texas at Austin in partial fulfillment of the requirements for the degree of

Master of Science in Engineering

As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks compared to the processor, it is necessary to use phase-locked loops (PLL) for multiplication and phase aligning of the clocks.

A PLL is composed of both digital and analog components and is not modeled well in a design environment for digital systems. There are design tools available that are more adept for doing PLL simulations; however, they can be very costly and are till not suitable for the way PLL's are used in computer systems. The goal of this report is to discuss current ways of simulation PLL's, then introduce a new simulator that is specifically designed for simulating PLL's used in computer systems.