Instruction Set Architecture

• Conventional 16-bit fixed-point DSP

  • 8 16-bit auxiliary/address registers (ar0-7)
  • Two 40-bit accumulators (a and b)
  • One 16 bit x 16 bit multiplier
  • Accumulator architecture

• Four busses (may be active each cycle)

  • Three read busses: program, data, coefficient
  • One write bus: writeback

• Memory blocks

  • ROM in 4k blocks
  • Dual-access RAM in 2k blocks
  • Single-access RAM in 8k blocks

• Two clock cycles per instruction cycle

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