*Introduction to System-Level Design*

Prof. Brian L. Evans

Embedded Signal
Processing Laboratory

Dept. of Electrical and Computer Engineering

The University of Texas at Austin, Austin, Texas 78712-1084

A common practice in industry is to use a style of specification that biases the possible implementation technology. Specifying an algorithm in C or VHDL would bias the implementation towards compiled code running on a programmable processor or hardware, respectively. It is not possible to convert all possible C programs into statically schedulable VHDL code because C is Turing equivalent, which means that C programs could have infinite state. Some specification languages, e.g. imperative programs such as C, force the designer to make several arbitrary choices about the sequential order of the subtasks. An inherent parallelism at a functional level is now hidden, and many good alternatives may be missed.

By decoupling the specification from implementation and using formal
mathematical models of computation for specification, we gain the ability
to perform fast simulation and efficient synthesis of complex heterogeneous
systems.
We model complex systems as a hierarchical composition of the simpler models
of computation.
Some of these simpler models of computation, such as types of finite
state machines, dataflow models, and synchronous/reactive models, have
finite state.
Because they have finite state, all analyses of the system can be
performed at compile-time.
For example, memory usage and execution time can be determined
*without* having to run the system.
These models can be overlaid on an implementation technology (such as
C or VHDL).

In the first half of the talk, we will discuss several issues in system-level design including cosimulation and codesign. We will survey different models of computation and communication for control, signal processing, and communications applications. In the second half of the talk, we will first describe dataflow modeling. Then, we will focus on the Synchronous Dataflow model, which can be statically scheduled. The Synchronous Dataflow model is determinate: the state of the system (the set of signals on all of the arcs) is not affected by the scheduling algorithm. Using the Synchronous Dataflow, we guarantee at compile time that a graph (program) is consistent and will not deadlock.

- Models of computation and communication (slides)
- Introduction to Dataflow Modeling (slides)
- Introduction to Synchronous Dataflow (notes)
- Synchronous Dataflow (notes)

Mail comments about this page to bevans@ece.utexas.edu.