EE382M.7 VLSI I (Spring 2009)

Unique Course No.: 16675

 

Instructor: Prof. David Z. Pan
Tue/Thu 12:30 – 2:00pm at RLM 5.112


Email: dpan@ece.utexas.edu, Phone: 512-471-1436
Office: ACES Building 5th floor, 5.434

Office hours: Tue/Thu 3-4pm, and by appointment

 

Course description:

We aim to study the process of implementing a digital system as a CMOS integrated circuit. The course will begin with a review of the basics of CMOS transistor operation and the manufacturing process for CMOS VLSI chips. We will then study in detail the problem of implementing logic gates in CMOS. Specifically, we will cover layout, design rules, and circuit families. Afterwards, we will examine techniques for timing and power analysis and clocking. We will also examine ways to optimize timing and power. This will be followed by an overview of datapath design, specifically adders and multipliers. We will also study memory arrays, including SRAM and DRAM cell and clock design. The course will conclude with a survey level treatment of various peripheral topics, including functional verification, test, design-for-test, electrical effects, and future trends. We may also have guest lecturers talk about real-world design practice.

 

Prerequisite:
This course is intended for ECE graduate students. A knowledge of Electrical Circuits (EE411 or equivalent), and Digital Logic Design (EE316 or its equivalent) is required.

 

Textbook:
 

  • N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition), 2005. Addison-Wesley.

 

Grading Policy: 

  • 10% homework
  • 35% three major labs
  • 30% two in-class midterms
  • 25% final project

 

Lecture Outline (tentative):

 

1. Introduction, CMOS Transistors

2. CMOS Fabrication and Layout

3. CMOS Logic

4. MOS Transistor Theory

5. DC and Transient Gate Characteristics

6. Logical Effort

7. Combinational Circuits

8. Design of Adders

9. Interconnects in CMOS Technology

10. Sequential Elements

11. Hardware Description Languages, Synthesis

12. Design Styles

13. Datapath Design

14. Memories

15. Dynamic CMOS Logic

16. Deep Submicron Issues

17. CAMs, ROMs, PLAs

18. Circuit Pitfalls

19. Manufacturing Test

20. Design for Testability

21. Design Verification

22. Packaging and I/O

23. Design for Low Power

24. Skew-Tolerant Design

25. Scaling

26. Future Directions

 

College of Engineering Drop/Add Policy: 

The Dean must approve adding or dropping courses after the fourth class day of the semester.

 

Students with Disabilities:  

The University of Texas at Austin provides upon request appropriate academic accommodations for qualified students with disabilities. For more information, contact the Office of the Dean of Students at 471-6259, 471-4641 TTY or the College of Engineering Director of Students with Disabilities at 471-4382.