#Number
TR-PDS-1995-012

#Title
Statistics on Concurrent Fault and Design Error Simulation

#Author
Brian C. Grayson, Saghir A. Shaikh, and Stephen A.  Szygenda


#Abstract
  Basic data of the nature presented here on fault and design error
  simulation processes have not been previously reported.  Experiments are
  performed on c_sim, a gate level concurrent simulator developed at the
  University of Texas at Austin. Three types of statistics are considered:
  event-based statistics, gate-evaluation statistics and memory
  requirements.  These statistics are important for design verification
  researchers and engineers for numerous reasons.  For example, they help
  simulator developers tune up or optimize their concurrent simulators.
  They also fulfill the increasing need for experimental data concerning
  design error simulation.  Most importantly, these statistics provide
  guidance to hardware accelerator designers in evaluating and comparing
  various design options.

#Bib
@TechReport{GSS95,
  author =       "Brian C. Grayson, Saghir A. Shaikh, and
                  Stephen A.  Szygenda",
  title =        "Statistics on Concurrent Fault and Design Error
                  Simulation",
  institution =  "Parallel and Distributed Systems Laboratory, ECE
                  Dept. University of Texas at Austin",
  year =         "1995",
  number =    "TR-PDS-1995-012",
  note =      "presented at the 1995 IEEE International Conference on
                  Computer Design:  VLSI in Computers and Processors (ICCD
                  1995)",
  note =      "available via ftp or WWW at maple.ece.utexas.edu
                  as technical report ECE-PDS-1995-012",
}