Embedded System Design and Modeling

ECE382N.23, Unique: 18090
Semester: Fall 2022

References

[1] K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.

[2] A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.

[3] E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.

[4] G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.

[5] T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.

[6] E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.

[7] W. Thies, M. Karczmarek, S. P. Amarasinghe, "StreamIt: A Language for Streaming Applications," International Conference on Compiler Construction (CC), March 2002.

[8] D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.

[9] L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.

[10] O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, "The Next Generation of Virtual Prototyping: Ulta-fast Yet Accurate Simulation of HW/SW Systems," Design, Automation and Test in Europe (DATE), March 2015.

[11] P. Derler, T. H. Feng, E. A. Lee, S. Matic, H.D. Patel, Y. Zheo, J. Zhou, PTIDES: A Programming Model for Distributed Real-Time Embedded Systems, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2008-72, May 2008.

[12] P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 5s, November 2014.

[13] G. Schirner, R. Dömer, "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.

[14] R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, P. Stenström., "The Worst-Case Execution-Time Problem - Overview of Methods and Survey of Tools," ACM Transactions on Embedded Computing Systems (TECS), vol. 7, no. 3, pp. 1-53, April 2008.

[15] L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.

[16] D. Lee, A. Gerstlauer, "Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 23, no. 3, pp. 30:1-30:25, February 2018.

[17] X. Zheng, L. K. John, A. Gerstlauer, "LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction," International Journal of Parallel Programming (IJPP), vol. 45, no. 6, pp. 1488-1514, December 2017.

[18] E. S. Alcorta, A. Gerstlauer, "Learning-based Phase-aware Multi-core CPU Workload Forecasting," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2022.

[19] A. K. Singh, M. Shafique, A. Kumar, J. Henkel, "Mapping on Multi/Many-core Systems: Survey of Current and Emerging Trends," Design Automation Conference (DAC), June 2013.

[20] M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.

[21] R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.

[22] A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.

Supplemental Information

Prof. Brian Evan's (UT Austin) lecture notes for EE382C Embedded Software Systems
Prof. Edward Lee's (UC Berkeley) lecture notes for EECS219D Concurrent Models of Computation
Prof. Lothar Thiele's (ETH Zürich) lecture notes on Hardware/Software Codesign
Prof. Hanxleden's (Kiel Univ., Germany) lecture notes on Synchronous Languages
- Additional lecture notes on the Semantics of Statecharts
Prof. Stephen Edwards' (Columbia Univ.) lecture notes for COMS W4995-02 Languages for Embedded System Design

Example Projects

Previous projects resulting from this class:
1. A. K. Ananda Kumar, A. Gerstlauer, "Learning-Based CPU Power Modeling," Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Canmore, Canada, September 2019.
2. K. M. Barijough, Z. Zhao, A. Gerstlauer, "Quality/Latency-Aware Real-time Scheduling of Distributed Streaming IoT Applications," ACM Transactions on Embedded Computing Systems (TECS), Special Issue on Embedded Systems Week (ESWEEK), International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2019.
3. K. Punniyamurthy, B. Boroujerdian, A. Gerstlauer, "GATSim: Abstract Timing Simulation of GPUs," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Lausanne, Switzerland, March 2017.
4. X. Zheng, P. Ravikumar, L. K. John, "Learning-based Analytical Cross-Platform Performance Prediction," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2015. (best paper award)
5. S. Lee, K. Saleem, J. Li, "Fine Grain Word Length Optimization for Dynamic Precision Scaling in DSP Systems," Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, October 2013. (best paper candidate)
6. A. Abdel-Hadi, J. Michel, S. Vishwanath, "Real-Time Optimization of Video Transmission in a Network of AAVs," Proceedings of the IEEE Vehicular Technology Conference (VTC), San Francisco, CA, September 2011.
7. J. Lin, A. Srivasta, B. L. Evans, "Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems," Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 2011.
8. A. Pedram, D. Craven, T. Amimeur, "Modeling Cache Effects at the Transaction Level," International Embedded Systems Symposium (IESS), Langenargen, Germany, September 2009. (best paper runner-up)
9. A. Banerjee, "Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices," International Embedded Systems Symposium (IESS), Langenargen, Germany, September 2009.
Publications resulting from projects in other classes (with often significant additional effort):
1. G. E. Allen and B. L. Evans, "Real-Time Sonar Beamforming on Workstations Using Process Networks and POSIX Threads," IEEE Transactions on Signal Processing, vol. 48, no. 3, pp. 921-926, March 2000.
2. G. E. Allen, P. E. Zucknick and B. L. Evans, "A Distributed Deadlock Detection and Resolution Algorithm for Process Networks," IEEE Int. Conference on Acoustics, Speech, and Signal Processing, Honolulu, HI, April 2007.
Project guidelines and ideas from Prof. Evans' Embedded Software class.

Design Language Documentation

SystemC
1. SystemC Environment Setup instructions
2. Accelera SystemC™ standards
3. IEEE Standard SystemC Reference Manual (IEEE 16666-2011)
4. A SystemC Quick Reference card
5. SystemC Training from Doulos (includes a brief SystemC Tutorial)
SpecC
Esterel
1. Introduction to Esterel
2. Esterel v5 Language Primer
3. The Esterel Language tutorial by Pascal Raymond, Verimag-CNRS (short version)
4. Using and Compiling Esterel tutorial by Prof. Stephen Edwards, Columbia University
5. Esterel V5 Syntax reference card

Reference Material

SpecC
- SpecC System at UC Irvine
- System-On-Chip Environment (SCE)
SystemC™
- Accellera
- Synopsys^®
- Mentor Graphics^®
Esterel
- Esterel.org (original Esterel Web pages at INRIA, and even older pages about the Esterel Language)
- Esterel Technologies^®
- Columbia Esterel Compiler (CEC)
- Collection of free Esterel programming tutorials
System-level design environments
- Ptolemy at UC Berkeley
- SystemCoDesigner at University of Erlangen-Nuremberg
- Daedalus at University of Amsterdam and Leiden University
- PeaCE and HOPES at Seoul National University
- Metropolis at UC Berkeley
Technical writing
- IEEE Authoring Tools and Templates including IEEE Transactions paper template.
- Prof. Stephen A. Edwards' guide on writing scholarly papers.
- Another guide for writing technical articles from Columbia University.
- Tips for writing technical papers from Stanford's InfoLab.

Links

http://www.ece.utexas.edu/~gerstl/ece382n_f22

[1]	K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.
[2]	A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.
[3]	E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.
[4]	G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.
[5]	T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.
[6]	E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.
[7]	W. Thies, M. Karczmarek, S. P. Amarasinghe, "StreamIt: A Language for Streaming Applications," International Conference on Compiler Construction (CC), March 2002.
[8]	D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.
[9]	L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
[10]	O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, "The Next Generation of Virtual Prototyping: Ulta-fast Yet Accurate Simulation of HW/SW Systems," Design, Automation and Test in Europe (DATE), March 2015.
[11]	P. Derler, T. H. Feng, E. A. Lee, S. Matic, H.D. Patel, Y. Zheo, J. Zhou, PTIDES: A Programming Model for Distributed Real-Time Embedded Systems, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2008-72, May 2008.
[12]	P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 5s, November 2014.
[13]	G. Schirner, R. Dömer, "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.
[14]	R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, P. Stenström., "The Worst-Case Execution-Time Problem - Overview of Methods and Survey of Tools," ACM Transactions on Embedded Computing Systems (TECS), vol. 7, no. 3, pp. 1-53, April 2008.
[15]	L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.
[16]	D. Lee, A. Gerstlauer, "Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 23, no. 3, pp. 30:1-30:25, February 2018.
[17]	X. Zheng, L. K. John, A. Gerstlauer, "LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction," International Journal of Parallel Programming (IJPP), vol. 45, no. 6, pp. 1488-1514, December 2017.
[18]	E. S. Alcorta, A. Gerstlauer, "Learning-based Phase-aware Multi-core CPU Workload Forecasting," ACM Transactions on Design Automation of Electronic Systems (TODAES), 2022.
[19]	A. K. Singh, M. Shafique, A. Kumar, J. Henkel, "Mapping on Multi/Many-core Systems: Survey of Current and Emerging Trends," Design Automation Conference (DAC), June 2013.
[20]	M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.
[21]	R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.
[22]	A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.