Embedded System Design and Modeling

EE382N.23, Unique: 16865 and 16869 (Professional MS)
Semester: Fall 2017

References

[1] K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.

[2] L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.

[3] W. Chen, X. Han, C.-W. Chang, R. Dömer, "Advances in Parallel Discrete Event Simulation for Electronic System-Level Design," IEEE Design & Test, vol. 3, no. 1, pp. 45-54, March 2012.

[4] W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.

[5] G. Berry, "The Esterel v5 Language Primer," Version v5_91, INRIA, France, June 2000.
[6] E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.

[7] G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.

[8] T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.

[9] M. Geilen, T. Basten, "Requirements on the execution of Kahn process networks", European Symposium on Programming Languages and Systems (ESOP), 2003.

[10] E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.

[11] S. S. Bhattacharyya, P. K. Murthy, E. A. Lee, "Synthesis of Embedded Software from Synchronous Dataflow Specifications," Journal of VLSI signal processing systems for signal, image and video technology, vol. 21, no. 1, pp. 151-166, June 1999.

[12] W. Thies, M. Karczmarek, S. P. Amarasinghe, "StreamIt: A Language for Streaming Applications," International Conference on Compiler Construction (CC), March 2002.

[13] D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.

[14] F. Vahid, S. Narayan, D. Gajski, "SpecCharts: A VHDL Front-End for Embedded Systems," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 14, no. 6, pp. 694-706, June 1995.
[15] A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.

[16] L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.

[17] O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, "The Next Generation of Virtual Prototyping: Ulta-fast Yet Accurate Simulation of HW/SW Systems," Design, Automation and Test in Europe (DATE), March 2015.

[18] Z. Zhao, A. Gerstlauer, L. K. John, "Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 2, pp. 299-312, February 2017.

[19] A. Gerstlauer, H. Yu, D. Gajski, "RTOS Modeling for System-Level Design," Design, Automation and Test in Europe (DATE) Conference, March 2003.

[20] P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computer Systems (TECS), 2014.

[21] A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1676-1687, September 2007.
[22] G. Schirner, R. Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.

[23] A. K. Singh, M. Shafique, A. Kumar, J. Henkel, "Mapping on Multi/Many-core Systems: Survey of Current and Emerging Trends," Design Automation Conference (DAC), June 2013.

[24] J. Lin, A. Gerstlauer, B. L. Evans, "Communication-Aware Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems," Journal of Signal Processing Systems, vol. 69, no. 3, December 2012.

[25] M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.

[26] L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.

[27] R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.

[28] A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.

Additional references and documents are available for download in the Files section of Canvas.

Projects

Previous projects resulting from this class:
1. K. Punniyamurthy, B. Boroujerdian, A. Gerstlauer, "GATSim: Abstract Timing Simulation of GPUs," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Lausanne, Switzerland, March 2017.
2. X. Zheng, P. Ravikumar, L. K. John, "Learning-based Analytical Cross-Platform Performance Prediction," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2015. (best paper award)
3. S. Lee, K. Saleem, J. Li, "Fine Grain Word Length Optimization for Dynamic Precision Scaling in DSP Systems," Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, October 2013. (best paper candidate)
4. A. Abdel-Hadi, J. Michel, S. Vishwanath, "Real-Time Optimization of Video Transmission in a Network of AAVs," Proceedings of the IEEE Vehicular Technology Conference (VTC), San Francisco, CA, September 2011.
5. J. Lin, A. Srivasta, B. L. Evans, "Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems," Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 2011.
6. A. Pedram, D. Craven, T. Amimeur, "Modeling Cache Effects at the Transaction Level," International Embedded Systems Symposium (IESS), Langenargen, Germany, September 2009. (best paper runner-up)
7. A. Banerjee, "Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices," International Embedded Systems Symposium (IESS), Langenargen, Germany, September 2009.
Publications resulting from projects in other classes (with often significant additional effort):
1. G. E. Allen and B. L. Evans, "Real-Time Sonar Beamforming on Workstations Using Process Networks and POSIX Threads," IEEE Transactions on Signal Processing, vol. 48, no. 3, pp. 921-926, March 2000.
2. G. E. Allen, P. E. Zucknick and B. L. Evans, "A Distributed Deadlock Detection and Resolution Algorithm for Process Networks," IEEE Int. Conference on Acoustics, Speech, and Signal Processing, Honolulu, HI, April 2007.
Project guidelines and ideas from Prof. Evans' Embedded Software class.

Documentation

SpecC
SCE
Esterel
1. Introduction to Esterel
2. The Esterel Language tutorial by Pascal Raymond, Verimag-CNRS (short version)
3. Using and Compiling Esterel tutorial by Prof. Stephen Edwards, Columbia University
4. Esterel V5 Syntax reference card

Related Courses

http://www.ece.utexas.edu/~gerstl/ee382n_f17

[1]	K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.
[2]	L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.
[3]	W. Chen, X. Han, C.-W. Chang, R. Dömer, "Advances in Parallel Discrete Event Simulation for Electronic System-Level Design," IEEE Design & Test, vol. 3, no. 1, pp. 45-54, March 2012.
[4]	W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.
[5]	G. Berry, "The Esterel v5 Language Primer," Version v5_91, INRIA, France, June 2000.
[6]	E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.
[7]	G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.
[8]	T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.
[9]	M. Geilen, T. Basten, "Requirements on the execution of Kahn process networks", European Symposium on Programming Languages and Systems (ESOP), 2003.
[10]	E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.
[11]	S. S. Bhattacharyya, P. K. Murthy, E. A. Lee, "Synthesis of Embedded Software from Synchronous Dataflow Specifications," Journal of VLSI signal processing systems for signal, image and video technology, vol. 21, no. 1, pp. 151-166, June 1999.
[12]	W. Thies, M. Karczmarek, S. P. Amarasinghe, "StreamIt: A Language for Streaming Applications," International Conference on Compiler Construction (CC), March 2002.
[13]	D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.
[14]	F. Vahid, S. Narayan, D. Gajski, "SpecCharts: A VHDL Front-End for Embedded Systems," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 14, no. 6, pp. 694-706, June 1995.
[15]	A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.
[16]	L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
[17]	O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, "The Next Generation of Virtual Prototyping: Ulta-fast Yet Accurate Simulation of HW/SW Systems," Design, Automation and Test in Europe (DATE), March 2015.
[18]	Z. Zhao, A. Gerstlauer, L. K. John, "Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 2, pp. 299-312, February 2017.
[19]	A. Gerstlauer, H. Yu, D. Gajski, "RTOS Modeling for System-Level Design," Design, Automation and Test in Europe (DATE) Conference, March 2003.
[20]	P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computer Systems (TECS), 2014.
[21]	A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1676-1687, September 2007.
[22]	G. Schirner, R. Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.
[23]	A. K. Singh, M. Shafique, A. Kumar, J. Henkel, "Mapping on Multi/Many-core Systems: Survey of Current and Emerging Trends," Design Automation Conference (DAC), June 2013.
[24]	J. Lin, A. Gerstlauer, B. L. Evans, "Communication-Aware Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems," Journal of Signal Processing Systems, vol. 69, no. 3, December 2012.
[25]	M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.
[26]	L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.
[27]	R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.
[28]	A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.