Embedded System Design and Modeling

EE382V, Unique: 17295
Semester: Fall 2008

References

[1]	D. Gajski, J. Zhu, and R. Doemer, "Essential Issues in Codesign," Technical Report ICS-97-26, University of California, Irvine, June 1997.
[2]	L. Lavagno, A. Sangiovanni-Vincentelli, E. Sentovich, "Models of Computation for Embedded System Design," in System-Level Synthesis, edited by A. Jerraya and J. Mermet, pp. 45-102, 1999.
[3]	R. Doemer, "The SpecC System-Level Design Language and Methodology, Part 1," Embedded Systems Conference, March 2002.
[4]	R. Doemer, A. Gerstlauer, P. Kritzinger, M. Olivarez, "The SpecC System-Level Design Language and Methodology, Part 2," Embedded Systems Conference, March 2002.
[5]	A. Gerstlauer, "SpecC Modeling Guidelines," Technical Report CECS-TR-02-16, University of California, Irvine, April 2002.
[6]	L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
[7]	R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.
[8]	A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.
[9]	M. Olivarez, B. Bailey, "Smart Speed Technology: Results of Modeling for Embedded Applications," White Paper, Freescale Semiconductor, July 2007.
[10]	E. J. Johnson, A. Gerstlauer, R. Doemer, "Efficient Debugging and Tracing of System Level Designs," Technical Report CECS-TR-07-05, University of California, Irvine, November 2007.
[11]	L. Cai, A. Gerstlauer, D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," Design Automation Conference (DAC), June 2004.
[12]	W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.
[13]	A. Gerstlauer, D. Shin, S. Abdi, P. Chandraiah, D. Gajski, "Design of a MP3 Decoder using the System-On-Chip Environment (SCE)," Technical Report CECS-TR-07-05, University of California, Irvine, November 2007.
[14]	S. Swan, "An Introduction to System Level Modeling in SystemC 2.0," Cadence Design Systems, Open SystemC Initiative (OSCI) Whitepaper, 2001.
[15]	L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.
[16]	A. Gerstlauer, H. Yu, D. Gajski, "RTOS Modeling for System-Level Design," Design, Automatin and Test in Europe (DATE), March 2003.
[17]	G. Schirner, A. Gerstlauer, R. Doemer, "Abstract, Multifaceted Modeling of Embedded Processors for System Level Design," Asia and South Pacific Design Automation Conference (ASPDAC), January 2007.
[18]	A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), September 2007.
[19]	A. Gerstlauer, G. Schirner, D. Shin, J. Peng, "Necessary and Sufficient Functionality and Parameters for SoC Communication," Technical Report CECS-TR-06-01 (internal), University of California, Irvine, May 2006.

Note: copies of all references are also available for download on the class' Electronic Reserves page at the UT libraries.
 

Documentation

1. SpecC Environment Setup instructions
2. SpecC Language Reference Manual, Version 2.0
3. System-On-Chip Environment (SCE) Setup instructions
4. System-On-Chip Environment (SCE Version 2.2.0 Beta): Tutorial
   • Errata for SCE Tutorial
5. SCE Specification Model Reference Manual
6. SystemC Environment Setup instructions
7. A SystemC Quick Reference card and a SystemC Quick Reference Guide
8. IEEE Standard SystemC^® Language Reference Manual
9. SystemC Training from Doulos (includes a brief SystemC Tutorial)
10. SystemC 2.0 Tutorial with emphasis on new features in Version 2.0 of the language
11. Online SystemC Training Course from Forte Design Systems (makers of hardware synthesis tools)
12. Another SystemC Tutorial: Part 1 and Part 2
     

Links

• SpecC
  • SpecC System at UC Irvine
  • SpecC Technology Open Consortium (STORC)
  • System-On-Chip Environment (SCE)
     
• SystemC™
  • Open SystemC Initiative (OSCI)
  • CoWare^®
     
• Other environments
  • Ptolemy at UC Berkeley
  • Metropolis at UC Berkeley
     
• Conferences
  • Design, Automation and Test in Europe (DATE)
  • International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS) as part of the Embedded Systems Week (ESWEEK)
  • Asia and South Pacific Design Automation Conference (ASPDAC)
  • Design Automation Conference (DAC)
     
• Article (proposal and report) preparation
  • IEEE Author Digital Tool Box including IEEE Transactions paper template.
     

Related Courses

• UT Austin
  • EE382V: System-On-Chip (SoC) Design
  • EE382C: Embedded Software Systems
     
• At other universities
  • Iowa State, Cpr E588: Embedded Computer Systems
  • UC Irvine, EECS222A: SoC Description and Modeling
  • UC Irvine, EECS222C: SoC Software Synthesis
  • UCLA, EE 201A: VLSI Architectures and Design Methods
  • UC Berkeley, EE249: Design of Embedded Systems: Models, Validation, and Synthesis
  • Columbia, W4995-02: Languages for Embedded System Design