System-on-a-Chip (SoC) Design

EE382V, Fall 2014

Lab #3

Due: 11:59pm, November 3, 2014

 

Instructions:

•     This lab is a team exercise.

•     Please use the discussion board of Canvas for Q&A.

•     All reports and code MUST be submitted to the digital assignment of Canvas.

 

1       Overview

The goals of this lab are to:

•     Use Xilinx's Vivado high-level synthesis (HLS) tool to synthesize the Viterbi decoder and generate Verilog or VHDL code at the register transfer level (RTL).

•     Validate the generated RTL code and compare the results with the reference C model.

•     Explore various architectural alternatives.

 

2       Tutorial

Follow the Vivado HLS tutorial given in the extra class session by Xilinx. Please refer to the following materials for additional information:

  1. Xilinx's Vivado HLS Tutorial (ug871), Chapters 1 through 8
  2. Vivado HLS user's guide (ug902)

 

3       Creating Standalone, Synthesizable Viterbi Code

Starting from your isolated Viterbi SystemC module in Lab #2, we will now create a standalone Viterbi function that can be fed into Vivado HLS for synthesis:

 

  1. Take the single, isolated Viterbi function or method that you created in Lab #2, split it out into a standalone, global C/C++ function (if not done so already) and modify the code, if necessary, such that Vivado HLS can synthesize this top-level function into a RTL description.
  2. Develop a C or C++ testbench to test your standalone Viterbi function.
  3. Compile and run the code to check if the decoder is functioning correctly.

 

Deliverables:

1)     A README file including how to compile, run and verify your design

2)     A makefile or script to compile and/or run your code

3)     All required C or C++ code

4)     Any golden input/output test files

Note: the TA should be able to run your main program and compare the results using the testbench you provide.

 

4       Synthesizing the Viterbi Decoder

We will now synthesize the standalone Viterbi functionality down to a cycle-by-cycle RTL description:

 

  1. On a 64-bit LRC machine, run 'module load xilinx/2014.2', and launch Vivado HLS by running 'vivado_hls'.

 

  1. Create a new Vivado HLS project for your design with following settings:
    1. Project name: hls_viterbi (or whatever you want)
    2. Location: wherever you want
    3. Top Function: the name of your top-level Viterbi function
    4. Design Files: add your design files that are supposed to be synthesized (no header files, but .c or .cpp files).
    5. TestBench Files: add your testbench files and input data files for test. These files are not synthesized.
    6. Solution Name: solution1 (or whatever you want). In a Vivado HLS project, you can create multiple solutions, and each can have different synthesis options. And you can compare the solutions in Vivado HLS environment.
    7. Clock Period: There is no requirement for this lab. A good starting point is 10 ns, but the target clock should eventually be one of the parameters driving optimizations.
    8. Part Selection:

•     RTL tool: Auto

•     Specify: Boards -> Filter with Family 'zynq' -> Select 'Zedboard'

 

  1. Start from a default architectural constraint, i.e. don't specify any architectural constraints (=synthesis directives) yet at this point. You will be exploring different architectural alternatives in the next part of this lab. Run C simulation, and check what happens.

 

  1. Run C synthesis. Note that the butterfly operations are already unrolled and flattened in the given Viterbi C source code. This will restrict the type of loop optimizations Vivado HLS can perform. You may want to modify the Viterbi code to wrap the butterflies into a loop in order to prepare for exploration of different loop optimizations later. Discuss the results of the synthesis report that is automatically shown in Vivado HLS after synthesis.

 

  1. Validate your RTL code running C/RTL co-simulation. Check the digital waveform, and confirm the correct Viterbi operation.

 

Deliverables:

1)     A write-up briefly explaining how your RTL Viterbi works and how you validated the RTL design.

 

5       Optimizing the Design

Freely explore at least 3 different architectural alternatives using various features offered by Vivado HLS (e.g. unrolling, pipelining, memory optimization, etc.) to come up with an optimal design. Discuss your approaches to different solutions and compare them in terms of various design metrics, i.e. area, latency, throughput, and operating clock frequency.

 

Deliverables:

2)     A README file including how to run and what to compare

3)     All required C or C++ code

4)     The directives.tcl files to synthesize/verify your design

You must submit N numbers of .tcl scripts for all N solutions you have come up with. The directives.tcl file you are required to submit is under the Solution_# directory. The TA should be able to synthesize and verify all your designs.

5)     Generated RTL code for each of the design alternatives

6)     A write-up in your lab report:

a.     Explain the approaches you have used for each solution.

b.    Comparison of synthesis results

c.     Discussion of the results

 

Lab Report Submission

Submit the following deliverables via Canvas:

  1. A write-up in PDF format (Part 3, 4, and 5)
  2. An archive in compressed file format (Part 3 and 5).

- Source code, scripts, and README files