1
Project Description
The class will be
assigned to teams to do the various components of an industry-strength system
design. The intent of the project is to do a HW/SW co-design of an embedded SoC. The design is a low power SOC implementation of the
public domain DRM (Digital Radio Mondiale) software implementation. The platform
will consist of an ARM processor, memory components, custom hardware
accelerators etc. The ARM processor was chosen because it is used for a
majority of the components developed for the target market. The teams will be
given a market requirements document (MRD) and will then generate a product
requirements document (PRD) which will be used to complete the implementation
of the DRM design.
The project activities include:
- Develop a PRD
for the HW/SW implementation of the low-power SOC
- Profile the
public domain software implementation to determine performance bottlenecks
(example in Lab1)
- Partition the
software into components which will run on the ARM processor and on the
hardware accelerator (example in Lab2)
- Convert the
hardware code to fixed point (example in Lab1)
- Verify that
the code maintains its target specification (example in Lab1 and Lab2)
- Synthesize
the hardware accelerator to RTL (example in Lab3)
- Prototype the
hardware accelerator on the FPGA
- Establish
proper communication between the software and hardware (example in Lab2
and the board tutorial below)
- Co-verify the
prototype HW/SW implementation (example in Lab2 and the board tutorial
below)
- Develop a
high-level performance and power model of the SoC
- Estimate the
timing, area and power consumption and validate product metrics described in
the product MRD
The main tasks for the final part
of the project are as follows:
- Integrate,
optimize and prototype the DRM SoC on the
ARM+FPGA board. Please refer to case study
for some initial guidance. You can come up with functions other than
Viterbi decoder to transform to a hardware accelerator. Please refer to
profiling results and develop your own hardware accelerator, if you want
to do so.
- Interface the
hardware accelerator to the ARM processor, and develop and optimize the
communication architecture.
- Implement the
remaining DRM functionality on the ARM processor and interface the ARM
software to the hardware accelerator
prototype in the FPGA.
2 Market
Requirements Document (MRD)
The MRD
for the DRM Receiver is derived from a combination of specifications for a PC based implementation and
from an integrated circuit developed at Texas Instruments.
Specifically, the cost metrics for the
project are:
-
Real-time operation
-
Utilize no more than 25% of a dual-core ARM
Cortex-A9 running at 667MHz
-
0.5mm² for accelerators
-
On board memory TBD
-
Additional system power for accelerators < 8mW
3
Product Requirements Document (PRD)
Some PRD examples:
4 Prototyping
Board
We are using an ARM- and FPGA-based development board for prototyping
our ASIC SoC design: