Embedded System Design and Modeling

EE382V, Unique: 17303
Semester: Spring 2014

References

[1] K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.

[2] L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.

[3] W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.

[4] E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.

[5] G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.

[6] T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.

[7] E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.

[8] D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.

[9] F. Vahid, S. Narayan, D. Gajski, "SpecCharts: A VHDL Front-End for Embedded Systems," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), June 1995.
[10] A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.

[11] R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.

[12] L. Cai, A. Gerstlauer, D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," Design Automation Conference (DAC), June 2004.

[13] L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.

[14] J. Lin, A. Gerstlauer, B. L. Evans, "Communication-Aware Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems," Journal of Signal Processing Systems, vol. 69, no. 3, December 2012.

[15] H. Topcuoglu, S. Hariri, M.-Y. Wu, "Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing," IEEE Transactions on Parallel and Distributed Systems, vol. 13, no. 3, pp. 260-274, March 2002.

[16] M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.

[17] L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.

[18] A. Gerstlauer, S. Chakravarty, M. Kathuria, P. Razaghi, Abstract System-Level Models for Early Performance and Power Exploration," Asia and South Pacific Design Automation Conference (ASP-DAC), January 2012.

[19] S. Chakravarty, Z. Zhao, A. Gerstlauer, "Automated, Retargetable Back-Annotation for Host-Compiled Performance and Power Modeling," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2013.

[20] P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computer Systems (TECS), 2014.

[21] A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1676-1687, September 2007.
[22] G. Schirner, R. Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.

[23] A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.

Additional references and documents are available for download on in the Course Documents section of Blackboard.

Projects

Previous projects resulting from this class:
1. S. Lee, K. Saleem, J. Li, "Fine Grain Word Length Optimization for Dynamic Precision Scaling in DSP Systems," Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, October 2013. (best paper candidate)
2. A. Abdel-Hadi, J. Michel, A. Gerstlauer, S. Vishwanath, "Real-Time Optimization of Video Transmission in a Network of AAVs," Proceedings of the IEEE Vehicular Technology Conference (VTC), San Francisco, CA, September 2011.
3. J. Lin, A. Srivasta, A. Gerstlauer, B. L. Evans, "Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems," Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 2011.
4. A. Pedram, D. Craven, T. Amimeur, "Modeling Cache Effects at the Transaction Level," International Embedded Systems Symposium (IESS), Langenargen, Germany, September 2009. (best paper runner-up)
5. A. Banerjee, "Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices," International Embedded Systems Symposium (IESS), Langenargen, Germany, September 2009.
Publications resulting from projects in other classes (with often significant additional effort):
1. G. E. Allen and B. L. Evans, "Real-Time Sonar Beamforming on Workstations Using Process Networks and POSIX Threads," IEEE Transactions on Signal Processing, vol. 48, no. 3, pp. 921-926, March 2000.
2. G. E. Allen, P. E. Zucknick and B. L. Evans, "A Distributed Deadlock Detection and Resolution Algorithm for Process Networks," IEEE Int. Conference on Acoustics, Speech, and Signal Processing, Honolulu, HI, April 2007.
Project guidelines and ideas from Prof. Evans' Embedded Software class.

Documentation

SpecC Environment Setup instructions
SpecC Language Reference Manual, Version 2.0
SpecC Modeling Guidelines
Debugging and Tracing of SpecC Designs
System-On-Chip Environment (SCE) Setup instructions
System-On-Chip Environment (SCE Version 2.2.0 Beta): Tutorial
- Errata for SCE Tutorial
- Report on Design of a GSM Vocoder using SpecC Methodology
SCE Specification Model Reference Manual
Design of a MP3 Decoder using the System-On-Chip Environment (SCE)
SystemC Environment Setup instructions
A SystemC Quick Reference card and a SystemC Quick Reference Guide
IEEE Standard SystemC^® Language Reference Manual
SystemC Training from Doulos (includes a brief SystemC Tutorial)
SystemC 2.0 Tutorial with emphasis on new features in Version 2.0 of the language
Online SystemC Training Course from Forte Design Systems (makers of hardware synthesis tools)
Another SystemC Tutorial: Part 1 and Part 2
OSCI SystemC TLM-2.0 Standards
TLM-2.0 in Action online video tutorial
Getting Started with SystemC TLM-2.0 from Doulos

Related Courses

http://www.ece.utexas.edu/~gerstl/ee382v_s14

[1]	K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.
[2]	L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.
[3]	W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.
[4]	E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.
[5]	G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.
[6]	T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.
[7]	E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.
[8]	D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.
[9]	F. Vahid, S. Narayan, D. Gajski, "SpecCharts: A VHDL Front-End for Embedded Systems," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), June 1995.
[10]	A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.
[11]	R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.
[12]	L. Cai, A. Gerstlauer, D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," Design Automation Conference (DAC), June 2004.
[13]	L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.
[14]	J. Lin, A. Gerstlauer, B. L. Evans, "Communication-Aware Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems," Journal of Signal Processing Systems, vol. 69, no. 3, December 2012.
[15]	H. Topcuoglu, S. Hariri, M.-Y. Wu, "Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing," IEEE Transactions on Parallel and Distributed Systems, vol. 13, no. 3, pp. 260-274, March 2002.
[16]	M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.
[17]	L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
[18]	A. Gerstlauer, S. Chakravarty, M. Kathuria, P. Razaghi, Abstract System-Level Models for Early Performance and Power Exploration," Asia and South Pacific Design Automation Conference (ASP-DAC), January 2012.
[19]	S. Chakravarty, Z. Zhao, A. Gerstlauer, "Automated, Retargetable Back-Annotation for Host-Compiled Performance and Power Modeling," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2013.
[20]	P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computer Systems (TECS), 2014.
[21]	A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1676-1687, September 2007.
[22]	G. Schirner, R. Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.
[23]	A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.