Publications

Books

D. D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, ISBN 978-1-4419-0503-1, September 2009. (slides/errata)
A. Rettberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Rammig (editors), Embedded System Design: Topics, Techniques and Trends, Springer, ISBN 978-0-387-72257-3, June 2007.
A. Gerstlauer, R. Dömer, J. Peng, D. D. Gajski, System Design: A Practical Guide with SpecC, Chinese Edition, Translated by J. Bian and H. Xue, Tsinghua University Press, China, ISBN 978-7-302-13289-9, January 2008.
A. Gerstlauer, R. Dömer, J. Peng, D. D. Gajski, System Design: A Practical Guide with SpecC, Japanese Edition, Translated by T. Kinoshita, SpecC Technology Open Consortium, Japan, June 2001.
A. Gerstlauer, R. Dömer, J. Peng, D. D. Gajski, System Design: A Practical Guide with SpecC, Kluwer Academic Publishers, Boston, MA, ISBN 0-7923-7387-1, June 2001.
D. D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao, SpecC: Specification Language and Methodology, Japanese Edition, Translated by T. Kinoshita, CQ Publishing, Japan, ISBN 4-7898-3353-4, December 2000, 328 pages.
D. D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, Boston, MA, ISBN 0-7923-7822-9, March 2000, 336 pages.

Book Chapters

Erika S. Alcorta, Philip Brisk, and Andreas Gerstlauer, "Machine Learning for System-Level Modeling," in Machine Learning Applications in Electronic Design Automation, edited by Haoxing Ren and Jiang Hu, Springer, ISBN 978-3-031-13073-1, 2022.
Kamyar Mirzazad Barijough, Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu, and Andreas Gerstlauer, "Exploiting Approximations in Real-Time Scheduling," in Approximate Computing Techniques: From Component- to Application-Level, edited by Alberto Bosio, Daniel Ménard and Olivier Sentieys, Springer, ISBN 978-3-030-94704-0, 2022.
Seogoo Lee and Andreas Gerstlauer, "Approximate High-Level Synthesis of Custom Hardware," in Approximate Circuits: Methodologies and CAD, edited by Sherief Reda and Muhammad Shafique, Springer, ISBN 978-3-319-99321-8, 2019.
Daniel Mueller-Gritschneder and Andreas Gerstlauer, "Host-Compiled Simulation," in Handbook of Hardware/Software Codesign, edited by Soonhoi Ha and Jürgen Teich, Springer, ISBN 978-94-017-7358-4, 2017.
Gunar Schirner, Andreas Gerstlauer, and Rainer Dömer, "SCE: System-On-Chip Environment," in Handbook of Hardware/Software Codesign, edited by Soonhoi Ha and Jürgen Teich, Springer, ISBN 978-94-017-7358-4, 2017.
Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, and Shuvra S. Bhattacharyya, "Introduction to Hardware/Software Codesign," in Handbook of Hardware/Software Codesign, edited by Soonhoi Ha and Jürgen Teich, Springer, ISBN 978-94-017-7358-4, 2017.
Vania Joloboff and Andreas Gerstlauer, "Virtual Prototyping of Embedded Systems: Speed and Accuracy Tradeoffs," in Cyber-Physical System Design from an Architecture Analysis Viewpoint, Communications of NII Shonan Meetings, edited by Shin Nakajima, Jean-Pierre Talpin, Masumi Toyoshima, and Huafeng Yu, Springer, ISBN 978-981-10-4435-9, 2017.
Seogoo Lee and Andreas Gerstlauer, "Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems," in VLSI-SoC: At the Crossroads of Emerging Trends, edited by Alex Orailoglu, H. Fatih Ugurdag, Luis MIguel Silveira, Martin Margala, and Ricardo Reis, Springer, ISBN 978-3-319-23798-5, October 2015.
Gunar Schirner, Rainer Dömer, and Andreas Gerstlauer, "High-Level Development, Modeling and Automatic Generation of Hardware-Dependent Software," in Hardware-Dependent Software: Principles and Practice, edited by Wolfang Ecker, Wolfgang Mueller, and Rainer Dömer, Springer, ISBN 978-1-4020-9435-4, January 2009.
Henning Zabel, Wolfgang Mueller, and Andreas Gerstlauer, "Accurate RTOS Modeling and Analysis with SystemC," in Hardware-Dependent Software: Principles and Practice, edited by Wolfang Ecker, Wolfgang Mueller, and Rainer Dömer, Springer, ISBN 978-1-4020-9435-4, January 2009.
Andreas Gerstlauer, Haobo Yu, and Daniel D. Gajski, "RTOS Modeling for System-Level Design," in Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, edited by Rudy Lauwereins and Jan Madsen, Springer, ISBN 978-1-4020-6487-6, March 2008.
Andreas Gerstlauer, Haobo Yu, and Daniel D. Gajski, "RTOS Modeling for System-Level Design," in Embedded Software for SoC, edited by Ahmed A. Jerraya, Sungjoo Yoo, Norbert Wehn, and Diederik Verkest, Kluwer Academic Publishers, ISBN 1-4020-7528-6, June 2003.
Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel D. Gajski, Wolfram Hardt, and Bernd Kleinjohann, "The Specification Language SpecC within the PARADISE Design Environment," in Architecture and Design of Distributed Embedded Systems, edited by Bernd Kleinjohann, Kluwer Academic Publishers, ISBN 0-7923-7345-6, April 2001.

Journal Papers

Erika S. Alcorta, Mahesh Madhav, Richard Afoakwa, Scott Tetrick, Neeraja J. Yadwadkar, and Andreas Gerstlauer, "Characterizing Machine Learning-based Runtime Prefetcher Selection," IEEE Compter Architecture Letters (CAL), May 2024. (preprint)
Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Andreas Gerstlauer, and Ali E. Yilmaz, "A Hierarchical Classification Method for High-Accuracy Instruction Disassembly with Near-Field EM Measurements," ACM Transactions on Embedded Computing Systems (TECS), vol. 23, no. 1, pp. 10:1–10:21, January 2024. (preprint)
Erika S. Alcorta Lozano and Andreas Gerstlauer, "Learning-based Phase-aware Multi-core CPU Workload Forecasting," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 28, no. 2, pp. 23:1–23:27, March 2023. (preprint)
Mochamad Asri and Andreas Gerstlauer, "CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Special Issue on Embedded Systems Week (ESWEEK), International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), vol. 41, no. 11, pp. 4325–4336, November 2022. (preprint)
Francisco Javier Hernandez Santiago, Honglan Jiang, Hussam Amrouch, Andreas Gerstlauer, Leibo Liu, and Jie Han, "Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 69, no. 11, pp. 4558–4571, November 2022.
Ajay Krishna Ananda Kumar, Sami Alsalamin, Hussam Amrouch, and Andreas Gerstlauer, "Machine Learning-Based Microarchitecture-Level Power Modeling of CPUs," IEEE Transactions on Computers (TC), vol. 72, no. 4, pp. 941–961, April, 2023. (preprint)
Furkan Aydin, Aydin Aysu, Mohit Tiwari, Andreas Gerstlauer, and Michael Orshansky, "Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols," ACM Transactions on Embedded Computing Systems (TECS), vol. 20, no. 6, pp. 110:1–110:22, November 2021.
Tanfer Alan, Andreas Gerstlauer, and Jörg Henkel, "Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, no. 6, pp. 1231–1243, April 2021. (preprint)
Rafael Stahl, Alexander Hoffman, Daniel Mueller-Gritschneder, Andreas Gerstlauer, and Ulf Schlichtmann, "DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices," International Journal of Parallel Programming (IJPP), vol. 49, no. 4, pp. 600–624, April 2021. (preprint)
Mochamad Asri, Dhairya Malhotra, Jiajun Wang, George Biros, Lizy K. John, and Andreas Gerstlauer, "Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods," IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 32, no. 8, pp. 2035–2048, February 2021. (preprint)
Sami Salamin, Martin Rapp, Jörg Henkel, Andreas Gerstlauer, and Hussam Amrouch, "Dynamic Power and Energy Management for NCFET-based Processors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Special Issue on Embedded Systems Week (ESWEEK), International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), vol. 30, no. 11, pp. 3361–3372, October 2020. (preprint)
Zhuoran Zhao, Kamyar Mirzazad Barijough, and Andreas Gerstlauer, "Network-level Design Space Exploration of Resource-constrained Networks-of-Systems," ACM Transactions on Embedded Computing Systems (TECS), vol. 19, no. 4, pp. 22:1–22:26, June 2020. (preprint)
Phillip Stanley-Marbell, Armin Alaghi, Michael Carbin, Eva Darulova, Lara Dolecek, Andreas Gerstlauer, Ghayoor Gillani, Djordje Jevdjic, Thierry Moreau, Mattia Cacciotti, Alexandros Daglis, Natalie Enright Jerger, Babak Falsafi, Sasa Misailovic, Adrian Sampson, and Damien Zufferey, "Exploiting Errors for Efficiency: A Survey from Circuits to Applications," ACM Computing Surveys (CSUR), vol. 53, no. 3, pp. 51:1–51:39, June 2020. (preprint)
Heesu Kim, Jongho Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi, and Hanmin Park, "Aging Compensation With Dynamic Computation Approximation," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 67, no. 4, pp. 1319–1332, April 2020.
Hussam Amrouch, Seyed Borna Ehsani, Andreas Gerstlauer, and Jörg Henkel, "On the Efficiency of Voltage Overscaling under Temperature and Aging Effects," IEEE Transactions on Computers (TC), vol. 68, no. 11, pp. 1647–1662, November 2019. (preprint)
Kamyar Mirzazad Barijough, Zhuoran Zhao, and Andreas Gerstlauer, "Quality/Latency-Aware Real-time Scheduling of Distributed Streaming IoT Applications," ACM Transactions on Embedded Computer Systems (TECS), Special Issue on Embedded Systems Week (ESWEEK), International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), vol. 18, no. 5s, pp. 83:1–83:23, October 2019. (preprint)
Zhuoran Zhao, Kamyar Mirzazad Barijough, and Andreas Gerstlauer, "DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Special Issue on Embedded Systems Week (ESWEEK), International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), vol. 37, no. 11, pp. 2348–2359, October 2018. (preprint)
Shuang Song, Xu Liu, Qinzhe Wu, Andreas Gerstlauer, Tao Li, and Lizy K. John, "Start Late or Finish Early: A Distributed Graph Processing System with Redundancy Reduction," Proceedings of the VLDB Endowment (PVLDB), vol. 12, no. 2, pp. 154–168, October 2018. (paper)
Seogoo Lee and Andreas Gerstlauer, "Data-Dependent Loop Approximations for Performance-Quality Driven High-level Synthesis," IEEE Embedded Systems Letters (ESL), vol. 10, no. 1, pp. 18–21, March 2018. (preprint)
Dongwook Lee and Andreas Gerstlauer, "Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 23, no. 3, pp. 30:1–30:25, February 2018. (preprint)
Sabine Francis and Andreas Gerstlauer, "A Reactive and Adaptive Data Flow Model For Network-of-System Specification," IEEE Embedded System Letters (ESL), vol. 9, no. 4, pp. 121–124, December 2017. (preprint)
Xinnian Zheng, Lizy K. John, and Andreas Gerstlauer, "LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction," International Journal of Parallel Programming (IJPP), vol. 45, no. 6, pp. 1488–1514, December 2017. (preprint)
Zhuoran Zhao, Andreas Gerstlauer, and Lizy K. John, "Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 2, pp. 299–312, February 2017. (preprint)
Parisa Razaghi and Andreas Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computer Systems (TECS), Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES), vol. 13, no. 5s, November 2014. (preprint)
Ardavan Pedram, John D. McCalpin, and Andreas Gerstlauer, "A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores," Journal of Signal Processing Systems (JSPS), Special Issue on Application Specific Processors and Architectures, vol. 77, no. 1–2, pp. 169–190, October 2014. (preprint)
Seogoo Lee, Andreas Gerstlauer, and Robert W. Heath, "Distributed Real-time Implementation of Interference Alignment with Analog Feedback," IEEE Transactions on Vehicular Technology (TVT), vol. 64, no. 8, pp. 3513–3525, September 2014. (preprint)
Ardavan Pedram, Andreas Gerstlauer, and Robert Geijn, "Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator," IEEE Transactions on Computers (TC), Special Section on Computer Arithmetic, vol. 63, no. 8, pp. 1854–1867, August 2014. (preprint)
Dylan Pfeifer, Jonathan Valvano, and Andreas Gerstlauer, "SimConnect and SimTalk for Distributed Cyber-Physical System Simulation," SIMULATION: Transactions of The Society for Modeling and Simulation International, vol. 89, no. 10, pp. 1254–1271, October 2013. (preprint)
Ku He, Andreas Gerstlauer, and Micheal Orshansky, "Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-based Systems," IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 23, no. 6, pp. 961–974, June 2013. (preprint)
Ardavan Pedram, Robert Geijn, and Andreas Gerstlauer, "Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures," IEEE Transactions on Computers (TC), Special Issue on Energy Efficient Computing, vol. 61, no. 12, pp. 1724–1736, December 2012. (preprint)
Jing Lin, Andreas Gerstlauer, and Brian L. Evans, "Communication-Aware Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems," Journal of Signal Processing Systems, vol. 69, no. 3, pp. 279–291, December 2012. (preprint)
Parisa Razaghi and Andreas Gerstlauer, "Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets," IEEE Embedded System Letters (ESL), vol. 4, no. 1, pp. 5–8, March 2012. (preprint)
Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, and Jürgen Teich, "Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs," Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC), vol. 5, no. 4, January 2011. (preprint)
Gunar Schirner, Andreas Gerstlauer, and Rainer Dömer, "Fast and Accurate Processor Models for Efficient MPSoC Design," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 15, no. 2, pp. 10:1–10:26, February 2010. (preprint)
Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, and Jürgen Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517–1530, October 2009. (preprint)
Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, and Daniel D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems, January 2008. (preprint)
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, and Daniel D. Gajski, "An Interactive Design Environment for C-based High-level Synthesis of RTL Processors," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 16, no. 4, pp. 466-475, April 2008.
Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, and Daniel D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1676-1687, September 2007.
Slim Ben Saoud, Andreas Gerstlauer, and Daniel D. Gajski, "Codesign Methodology of Real-Time Embedded Controllers for Electromechanical Systems," American Journal of Applied Sciences, vol. 2, no. 9, pp. 1331-1336, October 2005.

Conference Papers

Alexander Cathis, Ge Li, Shijia Wei, Michael Orshansky, Mohit Tiwari, and Andreas Gerstlauer, "SoK Paper: Power Side-Channel Malware Detection," Proceedings of the International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), Austin, TX, November 2024. (Best paper award)
Pranav Rama, Madison Threadgill, and Andreas Gerstlauer, "Distributed Convolutional Neural Network Training on Mobile and Edge Clusters," Proceedings of the International Embedded Systems Symposium (IESS), Gainsville, FL, October 2024.
Endri Taka, Dimitrios Gourounas, Andreas Gerstlauer, Diana Marculescu, and Aman Arora, "Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs," Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Orlando, FL, May 2024.
Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sánchez Lopera, Wolfgang Ecker, Siddharth Garg, and Jiang Hu, "Special Session: Machine Learning for Embedded System Design," Proceedings of the ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Hamburg, Germany, September 2023. (Invited paper)
James Boyle, Mark Plagge, Suma G. Cardwell, Frances S. Chance, and Andreas Gerstlauer, "Performance and Energy Simulation of Spiking Neuromorphic Architectures for Fast Exploration," Proceedings of the ACM International Conference on Neuromorphic Systems (ICONS), Santa Fe, NM, August 2023.
Dimitrios Gourounas, Bagus Hanindhito, Arash Fathi, Dimitar Trenev, Lizy K. John, and Andreas Gerstlauer, "FAWS: FPGA Acceleration of Large-Scale Wave Simulations," Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Porto, Portugal, July 2023.
Ahsan Saeed, Denis Hoornaert, Dakshina Dasari, Dirk Ziegenbein, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Andreas Gerstlauer, and Renato Mancuso, "Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs," Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS) (Leibniz International Proceedings in Informatics (LIPIcs)), Vienna, Austria, July 2023. (Outstanding paper award)
Erika S. Alcorta, Neeraja J. Yadwadkar, and Andreas Gerstlauer, "Lightweight ML-based Runtime Prefetcher Selection on Many-core Platforms," Proceedings of the Workshop on Machine Learning for Computer Architecture and Systems (MLArchSys), Orlando, FL, June 2023.
Jackson Farley and Andreas Gerstlauer, "MAFAT: Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference," Proceedings of the International Embedded Systems Symposium (IESS): Designing Modern Embedded Systems: Software, Hardware, and Applications (IFIP Advances in Information and Communication Technology (IFFIPAICT)), Lippstadt, Germany, November 2022.
Ge Li, Alexander Cathis, Andrew Lu, Shijia Wei, Ross Brown, Alexander Liu, Mohit Tiwari, Andreas Gerstlauer, and Michael Orshansky, "Power-based Malware Detection in Linux Boot," Proceedings of the Industrial Control System Security (ICSS) Workshop, Austin, TX, December 2022.
Aditya Thimmaiah, Vishnuvardhan V. Iyer, Andreas Gerstlauer, and Michael Orshansky, "High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2022.
Ahsan Saeed, Dakshina Dasari, Dirk Ziegenbein, Varun Rajasekaran, Falk Rehm, Michael Pressler, Arne Hamann, Daniel Mueller-Gritschneder, Andreas Gerstlauer, and Ulf Schlichtmann, "Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores," Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Milano, Italy, May 2022.
Erika S. Alcorta and Andreas Gerstlauer, "Learning-Based Workload Phase Classification and Prediction Using Performance Monitoring Counters," Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), virtual conference, September 2021. (Best paper award)
Ahsan Saeed, Daniel Mueller-Gritschneder, Falk Rehm, Arne Hamann, Dirk Ziegenbein, Ulf Schlichtmann, and Andreas Gerstlauer, "Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores," Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), virtual conference, September 2021.
Bagus Hanindhito, Ruihao Li, Arash Fathi, Karan Govil, Dimitar Trenev, Andreas Gerstlauer, and Lizy K. John, "Wave-PIM: Accelerating Wave Simulation Using Processing-in-Memory," Proceedings of the IEEE International Conference on Parallel Processing (ICPP), virtual conference, August 2021.
Erika S. Alcorta, Pranav Rama, Aswin Ramachandran, and Andreas Gerstlauer, "Phase-Aware CPU Workload Forecasting," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), virtual conference, July 2021.
Qinzhe Wu, Jonathan Beard, Ashen Ekanayake, Andreas Gerstlauer, and Lizy K. John, "Virtual-Link: A Scalable Multi-Producer, Multi-Consumer Message Queue Architecture for Cross-Core Communication," Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS), virtual conference, May 2021. (preprint)
Georgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, and Jörg Henkel, "Approximate Computing for ML: State-of-the-art, Challenges and Visions," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), virtual conference, January 2021. (Invited paper)
Kishore Punniyamurthy and Andreas Gerstlauer, "TAFE: Thread Address Footprint Estimation for Capturing Data/Thread Locality in GPU Systems," Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), virtual conference, October 2020.
Sami Salamin, Martin Rapp, Hussam Amrouch, Andreas Gerstlauer, and Jörg Henkel, "Energy Optimization in NCFET-based Processors," Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), virtual conference, May 2020.
Tanfer Alan, Andreas Gerstlauer, and Jörg Henkel, "Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation," Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), virtual conference, May 2020.
Mochamad Asri, Curtis Dunham, Roxana Rusitoru, Andreas Gerstlauer, and Jonathan Beard, "The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload," Proceedings of the Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), Västerås, Sweden, March 2020.
Kishore Punniyamurthy and Andreas Gerstlauer, "Off-Chip Congestion Management for GPU-based Non-Uniform Processing-in-Memory Networks," Proceedings of the Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), Västerås, Sweden, March 2020.
Kishore Punniyamurthy, Shomit Das, and Andreas Gerstlauer, "Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs," Proceedings of the IEEE International Conference on VLSI Design and Embedded Systems (VLSID), Bengaluru, India, January 2020.
Ajay Krishna Ananda Kumar and Andreas Gerstlauer, "Learning-Based CPU Power Modeling," Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Canmore, Canada, September 2019.
Rafael Stahl, Zhuoran Zhao, Daniel Mueller-Gritschneder, Andreas Gerstlauer, and Ulf Schlichtmann, "Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2019.
Jongho Kim, Heesu Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, and Kiyoung Choi, "Aging Gracefully with Approximation," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Sapparo, Japan, May 2019.
Shijia Wei, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, and Mohit Tiwari, "Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems," Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tysons Corner, VA, May 2019. (Best paper runner-up)
Joseph Whitehouse, Qinzhe Wu, Shuang Song, Eugene John, Andreas Gerstlauer, and Lizy K. John, "A Study of Core Utilization and Residency in Heterogeneous Smart Phone Architectures," Proceedings of the ACM/SPEC International Conference on Performance Engineering (ICPE), Mumbai, India, April 2019.
Ahmed Abdelhadi, Andreas Gerstlauer, and Sriram Vishwanath, "Horus Testbed: Implementation of Real-Time Video Streaming Protocols," Proceedings of the IEEE International Systems Conference (SysCon), Orlando, FL, April 2019.
Ahmed Abdelhadi, Andreas Gerstlauer, and Sriram Vishwanath, "Real-Time Rate Distortion Optimized and AdaptiveLow Complexity Algorithms for Video Streaming," Proceedings of the IEEE International Systems Conference (SysCon), Orlando, FL, April 2019.
Behzad Boroujerdian, Hussam Amrouch, Jörg Henkel, and Andreas Gerstlauer, "Trading Off Temperature Guardbands via Adaptive Approximations," Proceedings of the IEEE International Conference on Computer Design (ICCD), Orlando, FL, October 2018.
Wenxiao Yu, Jacob Kornerup, and Andreas Gerstlauer, "MASES: Mobility And Slack Enhanced Scheduling For Latency-Optimized Pipelined Dataflow Graphs," Proceedings of the International Workshop on Software and Compilers for Embedded Systems (SCOPES), St. Goar, Germany, May 2018.
Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer, and Michael Orshansky, "Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols," Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, May 2018. (Best paper runner-up)
Reena Panda, Xinnian Zheng, Andreas Gerstlauer, and Lizy K. John, "CAMP: Accurate Modeling of Core and Memory Locality for Proxy Generation of Big-data Applications," Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, March 2018. (Best paper candidate)
Wooseok Lee, Reena Panda, Dam Sunwoo, Jose Joao, Andreas Gerstlauer, and Lizy K. John, "BUQS: Battery- and User-aware QoS Scaling for Interactive Mobile Devices," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju Island, South Korea, January 2018.
Kishore Punniyamurthy and Andreas Gerstlauer, "Exploring Non-Uniform Processing In-Memory Architectures," Proceedings of the Workshop on Hardware/Software Techniques for Minimizing Data Movement (MinMove), Portland, OR, September 2017.
Zhuoran Zhao, Vasileios Tsoutsouras, Dimitrios Soudris, and Andreas Gerstlauer, "Network/System Co-Simulation for Design Space Exploration of IoT Applications," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2017.
Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, and Jörg Henkel, "Towards Aging-Induced Approximations," Proceedings of the ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2017. (Best paper candidate)
Reena Panda, Xinnian Zheng, Jiajun Wang, Andreas Gerstlauer, and Lizy K. John, "Statistical Pattern Based Modeling of GPU Memory Access Streams," Proceedings of the ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2017.
Wooseok Lee, Dam Sunwoo, Andreas Gerstlauer, and Lizy K. John, "Cloud-guided QoS and Energy Management for Mobile Interactive Web Applications," Proceedings of the IEEE/ACM International Conference on Mobile Software Engineering and Systems (MobileSoft), Buenos Aires, Argentina, May 2017.
Wooseok Lee, Dam Sunwoo, Christopher D. Emmons, Andreas Gerstlauer, and Lizy K. John, "Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs," Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, May 2017.
Shuang Song, Raj Desikan, Mohamad Barakat, Sridhar Sundaram, Andreas Gerstlauer, and Lizy K. John, "Fine-Grain Program Snippets Generator for Mobile Core Design," Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, May 2017.
Xinnian Zheng, Shuang Song, Haris Vikalo Lizy K. John, and Andreas Gerstlauer, "Sampling-Based Binary-Level Cross-Platform Performance Estimation," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Lausanne, Switzerland, March 2017. (Best paper candidate)
Kishore Punniyamurthy, Behzad Boroujerdian, and Andreas Gerstlauer, "GATSim: Abstract Timing Simulation of GPUs," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Lausanne, Switzerland, March 2017.
Seogoo Lee, Lizy K. John, and Andreas Gerstlauer, "High-Level Synthesis of Approximate Hardware under Joint Precision and Voltage Scaling," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Lausanne, Switzerland, March 2017.
Shuang Song, Xinnian Zheng, Andreas Gerstlauer, and Lizy K. John, "Fine-grained Power Analysis of Emerging Graph Processing Workloads for Cloud Operations Management," Proceedings of the IEEE International Conference on Big Data (BigData): Workshop on Big Data for Cloud Operations Management (BDCOM), Washington, DC, December 2016.
Dylan Pfeifer, Andreas Gerstlauer, and Jonathan Valvano, "Adaptive Resolution Control in Distributed Cyber-Physical System Simulation," Proceedings of the Winter Simulation Conference (WSC), Arlington, VA, December 2016.
Shuang Song, Meng Li, Xinnian Zheng, Jee Ho Ryoo, Reena Panda, Michael LeBeane, Andreas Gerstlauer, and Lizy K. John, "Proxy-Guided Load Balancing of Graph Processing Workloads on Heterogeneous Clusters," Proceedings of the IEEE International Conference on Parallel Processing (ICPP), Philadelphia, PA, August 2016.
Jiajun Wang, Ahmed Khawaja, George Biros, Andreas Gerstlauer, and Lizy K. John, "Optimizing GPGPU Kernel Summation for Performance and Energy Efficiency," Proceedings of the IACC International Conference on Parallel Processing Workshops (ICPPW): International Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications (HUCAA), Philadelphia, PA, August 2016.
Mochamad Asri, Ardavan Pedram, Lizy K. John, and Andreas Gerstlauer, "Simulator Calibration for Accelerator-Rich Architecture Studies," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2016.
Reena Panda, Xinnian Zheng, Shuang Song, Jee Ho Ryoo, Michael LeBeane, Andreas Gerstlauer, and Lizy K John, "Genesys: Automatically Generating Representative Training Sets for Predictive Benchmarking," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2016.
Xinnian Zheng, Lizy K. John, and Andreas Gerstlauer, "Accurate Phase-Level Cross-Platform Power and Performance Estimation," Proceedings of the ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2016. (Best paper award)
Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, and Jörg Henkel, "Reliability-Aware Design to Suppress Aging," Proceedings of the ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2016.
Seogoo Lee, Dongwook Lee, Kyungtae Han, Taemin Kim, Emily Shriver, Lizy K. John, and Andreas Gerstlauer, "Statistical Quality Modeling of Approximate Hardware," Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 2016.
Dongwook Lee, Taemin Kim, Kyungtae Han, Yatin Hoskote, Lizy K. John, and Andreas Gerstlauer, "Learning-Based Power Modeling of System-Level Black-Box IPs," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2015.
Wooseok Lee, Youngchun Kim, Jee Ho Ryoo, Dam Sunwoo, Andreas Gerstlauer, and Lizy K. John, "PowerTrain: A Learning-based Calibration of McPAT Power Models," Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Rome, Italy, July 2015.
Xinnian Zheng, Pradeep Ravikumar, Lizy K. John, and Andreas Gerstlauer, "Learning-based Analytical Cross-Platform Performance Prediction," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2015. (Best paper award)
Dongwook Lee, Lizy K. John, and Andreas Gerstlauer, "Dynamic Power and Performance Back-Annotation for Fast and Accurate Functional Hardware Simulation," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, March 2015.
Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, and Simranjit Sing, "The Next Generation of Virtual Prototyping: Ultra-fast Yet Accurate Simulation of HW/SW Systems," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, March 2015.
Ahmed Khawaja, Jiajun Wang, Dhairya Malhotra, Andreas Gerstlauer, George Biros, and Lizy K. John, "Performance Analysis of HPC Applications with Irregular Tree Data Structures," Proceedings of the IEEE International Conference on Parallel and Distributed Systems (ICPADS), Hsinchu, Taiwan, December 2014.
Jin Miao, Andreas Gerstlauer, and Michael Orshansky, "Multi-Level Approximate Logic Synthesis under General Error Constraints," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2014.
Darshan Gandhi, Andreas Gerstlauer, and Lizy John, "FastSpot: Host-Compiled Thermal Estimation for Early Design Space Exploration," Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 2014.
Jin Miao, Andreas Gerstlauer, and Michael Orshansky, "Approximate Logic Synthesis under General Error Magnitude and Frequency Constraints," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2013.
Seogoo Lee and Andreas Gerstlauer, "Fine Grain Word Length Optimization for Dynamic Precision Scaling in DSP Systems," Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, October 2013. (Best paper candidate)
Suhas Chakravarty, Zhuoran Zhao, and Andreas Gerstlauer, "Automated, Retargetable Back-Annotation for Host-Compiled Performance and Power Modeling," Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Montreal, Canada, October 2013.
Artur Mariano, Dongwook Lee, Andreas Gerstlauer, and Derek Chiou, "Hardware and Software Implementations of Prim's Algorithm for Efficient Minimum Spanning Tree Computation," Proceedings of the International Embedded Systems Symposium (IESS): Embedded Systems: Design, Analysis and Verification (IFIP Advances in Information and Communication Technology (IFFIPAICT)), Paderborn, Germany, June 2013.
Hyungman Park and Andreas Gerstlauer, "Toward a Fast Stochastic Simulation Processor for Biochemical Reaction Networks," Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, June 2013.
Ardavan Pedram, John McCalpin, and Andreas Gerstlauer, "Transforming A Linear Algebra Core to An FFT Accelerator," Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, June 2013.
Parisa Razaghi and Andreas Gerstlauer, "Multi-Core Cache Hierarchy Modeling for Host-Compiled Performance Simulation," Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), Austin, TX, June 2013.
Dylan Pfeifer, Andreas Gerstlauer, and Jonathan Valvano, "Dynamic Resolution in Distributed Cyber-Physical System Simulation," Proceedings of the ACM SIGSIM Conference on Principles of Advanced Discrete Simulation (PADS), Montreal, Canada, May 2013.
Ardavan Pedram, Andreas Gerstlauer, and Robert Geijn, "Floating Point Architecture Extensions for Optimized Matrix Factorization," Proceedings of the IEEE Symposium on Computer Arithmetic (ARITH21), Austin, TX, April 2013.
Ku He, Andreas Gerstlauer, and Michael Orshansky, "Low-Energy Digital Filter Design Based on Controlled Timing Error Acceptance," Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2013.
Jin Miao, Ku He, Andreas Gerstlauer, and Michael Orshansky, "Modeling and Synthesis of Quality-Energy Optimal Approximate Adders," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2012.
Jackson W. Massey, Jonathan Starr, Seogoo Lee, Dongwook Lee, Andreas Gerstlauer, and Robert W. Heath, "Implementation of a Real-Time Wireless Interference Alignment Network," Proceedings of the Asilomar Conference on Signals, Systems and Computers (ASCSSC), Pacific Grove, CA, November 2012. (Invited paper)
Dongwook Lee, Hyungman Park, and Andreas Gerstlauer, "Synthesis of Optimized Hardware Transactors from Abstract Communication Specifications," Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Tampere, Finland, October 2012.
Ardavan Pedram, Andreas Gerstlauer, and Robert Geijn, "On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators," Proceedings of the IEEE/IFIP International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), New York, NY, October 2012.
Ardavan Pedram, Syed Zohaib Gilani, Nam Sung Kim, Robert Geijn, Mike Schulte, and Andreas Gerstlauer, "A Linear Algebra Core Design For Efficient Level-3 BLAS," Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Delft, The Netherlands, July 2012.
Ku He, Andreas Gerstlauer, and Michael Orshansky, "Low-Energy Signal Processing using Circuit-Level Timing Error Acceptance," Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Austin, TX, May 2012. (Invited paper)
Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, and Parisa Razaghi, "Abstract System-Level Models for Early Performance and Power Exploration," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, January 2012. (Invited paper)
Parisa Razaghi and Andreas Gerstlauer, "Automatic Timing Granularity Adjustment for Host-Compiled Software Simulation," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, January 2012.
Dylan Pfeifer and Andreas Gerstlauer, "Expression-Level Parallelism for Distributed Spice Circuit Simulation," Proceedings of the IEEE/ACM International Symposium on Distributed and Real Time Applications (DS-RT), Manchester, United Kingdom, September 2011.
Martha Salome Lopez, Andreas Gerstlauer, Alfonso Avila, and Sergio O. Martinez-Chapa, "A Programmable and Configurable Multi-port System-on-Chip for Stimulating Electrokinetically-Driven Microfluidic Devices," Proceedings of the International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Boston, MA, September 2011.
Ahmed Abdel-Hadi, Jonas Michel, Andreas Gerstlauer, and Sriram Vishwanath, "Real-Time Optimization of Video Transmission in a Network of AAVs," Proceedings of the IEEE Vehicular Technology Conference (VTC), San Francisco, CA, September 2011.
Ardavan Pedram, Andreas Gerstlauer, and Robert Geijn, "A High-Performance, Low-Power Linear Algebra Core," Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Santa Monica, CA, September 2011.
Jing Lin, Akshaya Srivasta, Andreas Gerstlauer, and Brian L. Evans, "Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems," Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic, May 2011.
Parisa Razaghi and Andreas Gerstlauer, "Host-Compiled Multicore RTOS Simulator for Embedded Real-Time Software Development," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, May 2011.
Ku He, Andreas Gerstlauer, and Michael Orshansky, "Controlled Timing-Error Acceptance for Low Energy IDCT Design," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, May 2011.
Rainer Dömer, Weiwei Chen, Xu Han, and Andreas Gerstlauer, "Multi-Core Parallel Simulation of System-Level Description Languages," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2011. (Invited paper)
Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, and Jürgen Teich, "A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2010.
Andreas Gerstlauer, "Host-Compiled Simulation of Multi-Core Platforms," Proceedings of the IEEE/IFIP International Symposium on Rapid System Prototyping (RSP), Washington, DC, June 2010. (Invited paper)
Andreas Gerstlauer and Gunar Schirner, "Platform Modeling for Exploration and Synthesis," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, January 2010. (Invited paper)
Gunar Schirner, Andreas Gerstlauer, and Rainer Dömer, "System-Level Development of Embedded Software," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, January 2010. (Invited paper)
Ardavan Pedram, David Craven, Tileli Amimeur, and Andreas Gerstlauer, "Modeling Cache Effects at the Transaction Level," Proceedings of the International Embedded Systems Symposium (IESS): Analysis, Architectures and Modeling of Embedded Systems (IFIP Advances in Information and Communication Technology (IFFIPAICT)), Langenargen, Germany, September 2009. (Best paper runner-up)
Amal Banerjee and Andreas Gerstlauer, "Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices," Proceedings of the International Embedded Systems Symposium (IESS): Analysis, Architectures and Modeling of Embedded Systems (IFIP Advances in Information and Communication Technology (IFFIPAICT)), Langenargen, Germany, September 2009.
Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, and Yuuji Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Proceedings of the ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, July 2008. (invited paper)
Gunar Schirner, Andreas Gerstlauer, and Rainer Dömer, "Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, January 2008.
Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, and Rainer Dömer, "Embedded Software Development in a System-Level Design Flow," Embedded System Design: Topics, Techniques and Trends, International Embedded Systems Symposium (IESS), Irvine, CA, edited by Achim Rettberg, Mauro Zanella, Rainer Dömer, Andreas Gerstlauer, and Franz Rammig, Springer, ISBN 978-0-387-72257-3, June 2007.
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, and Daniel D. Gajski, "An Interactive Design Environment for C-based High-Level Synthesis," Embedded System Design: Topics, Techniques and Trends, International Embedded Systems Symposium (IESS), Irvine, CA, edited by Achim Rettberg, Mauro Zanella, Rainer Dömer, Andreas Gerstlauer, and Franz Rammig, Springer, ISBN 978-0-387-72257-3, June 2007.
Gunar Schirner, Andreas Gerstlauer, and Rainer Dömer, "Abstract, Multifaceted Modeling of Embedded Processors for System Level Design," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2007.
Rainer Dömer, Andreas Gerstlauer, and Dongwan Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," Proceedings of the International SoC Design Conference (ISOCC), Seoul, Korea, October 2006.
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, and Daniel D. Gajski, "Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration," Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Seoul, Korea, October 2006.
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, and Daniel D. Gajski, "Automatic Generation of Communication Architectures," From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), Manaus, Brazil, edited by Achim Rettberg, Mauro C. Zanella, and Franz Rammig, Springer, ISBN 0-387-27557-6, September 2005.
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, and Daniel D. Gajski, "Automatic Network Generation for System-On-Chip Communication Design," Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New Jersey, NJ, September 2005.
Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, and Daniel D. Gajski, "System-Level Communication Modeling for Network-On-Chip Synthesis," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, January 2005.
Lukai Cai, Andreas Gerstlauer, and Daniel D. Gajski, "Multi-Metric and Multi-Entity Characterization of Applications for Early System Design Exploration," Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, January 2005.
Lukai Cai, Andreas Gerstlauer, and Daniel D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," Proceedings of the ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 2004.
Haobo Yu, Andreas Gerstlauer, and Daniel Gajski, "RTOS Scheduling in Transaction Level Models," Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign & System Synthesis (CODES+ISSS), Newport Beach, CA, October 2003.
Andreas Gerstlauer, Haobo Yu, and Daniel D. Gajski, "RTOS Modeling for System-Level Design," Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, March 2003.
Andreas Gerstlauer and Daniel D. Gajski, "System-Level Abstraction Semantics," Proceedings of the International Symposium on System Synthesis (ISSS), Kyoto, Japan, October 2002.
Wolfgang Mueller, Rainer Dömer, and Andreas Gerstlauer "The Formal Execution Semantics of SpecC," Proceedings of International Symposium on System Synthesis (ISSS), Kyoto, Japan, October 2002.
Slim Ben Saoud, Daniel D. Gajski, and Andreas Gerstlauer, "Co-design of Emulators for Power electric Processes Using SpecC Methodology," Proceedings 28th Annual Conference of the IEEE Industrial Electronics Society, Sevilla, Spain, November 2002.
Slim Ben Saoud, Daniel D. Gajski, and Andreas Gerstlauer, "Co-design of Embedded Controllers for Power Electronics and Electric Systems," Proceedings of the IEEE International Symposium on Intelligent Control, Vancouver, Canada, October 2002.
Rainer Dömer, Andreas Gerstlauer, and Daniel Gajski, "SpecC Methodology for High-Level Modeling," 9th IEEE/DATC Electronic Design Processes Workshop, Monterey, April 2002.
Andreas Gerstlauer, Shuqing Zhao, Daniel Gajski, and Arkady Horak, "SpecC System-Level Design Methodology Applied to the Design of a GSM Vocoder," Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Kyoto, Japan, April 2000.

Technical Reports

Pranav Rama, Andreas Gerstlauer, "Distributed Convolutional Neural Network Training on Resource-Constrained Mobile and Edge Clusters," CERC, UT Austin, Technical Report UT-CERC-24-02, May 2024.
Madison Threadgill, Andreas Gerstlauer, "A Survey of Distributed Learning in Cloud, Mobile, and Edge Settings," CERC, UT Austin, Technical Report UT-CERC-24-01, May 2024.
Jackson Farley, Andreas Gerstlauer, "Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference," CERC, UT Austin, Technical Report UT-CERC-21-01, May 2021.
Ajay Krishna Ananda Kumar, Andreas Gerstlauer, "Learning-Based Architecture-Level Power Modeling of CPUs," CERC, UT Austin, Technical Report UT-CERC-20-01, June 2020.
Malek Srour, Andreas Gerstlauer, "Data-Dependent Cycle-Accurate Power Modeling of RTL IPs Using Machine Learning," CERC, UT Austin, Technical Report UT-CERC-18-01, May 2018.
Wooseok Lee, Dam Sunwoo, Christopher D. Emmons, Andreas Gerstlauer, Lizy John, "Exploring Opportunities for Heterogeneous-ISA Core Architectures in High-Performance Mobile SoCs," CERC, UT Austin, Technical Report UT-CERC-17-01, March 2017.
Abhishek Das, Andreas Gerstlauer, "simCUDA: A C++ based CUDA Simulation Framework," CERC, UT Austin, Technical Report UT-CERC-16-01, May 2016.
Wenxiao Yu, Andreas Gerstlauer, "MASES: Mobility And Slack Enhanced Scheduler For Synchronous Dataflow Graphs," CERC, UT Austin, Technical Report UT-CERC-15-01, May 2015.
Wei-Cheng Su, Parisa Razaghi, Ashmita Sinha, Andreas Gerstlauer, "Design of Flexible Audio Processing Platforms using the System-on-Chip Environment," CERC, UT Austin, Technical Report UT-CERC-12-06, August 2012.
Manan Kathuria, Andreas Gerstlauer, "A Framework for Automation of System-Level Design Space Exploration," CERC, UT Austin, Technical Report UT-CERC-12-05, June 2012.
Ardavan Pedram, Andreas Gerstlauer, Robert van de Geijn, "Co-Design Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures," CERC, UT Austin, Technical Report UT-CERC-12-02, October 2011.
Arindam Goswami, Andreas Gerstlauer, "ExtractCFG: A Framework to Enable Accurate Timing Back Annotation of C Language Source Code," CERC, UT Austin, Technical Report UT-CERC-11-02, August 2011.
Hyungman Park, Xiaohu Shen, Haris Vikalo, Andreas Gerstlauer, "Algorithm/Architecture Co-Design of a Stochastic Simulation System-on-Chip ," CERC, UT Austin, Technical Report UT-CERC-11-01, February 2011.
Ardavan Pedram, Andreas Gerstlauer, Robert van de Geijn, "Towards a High-Performance, Low-Power Linear Algebra Processor," CERC, UT Austin, Technical Report UT-CERC-10-03, September 2010.
Pablo Salinas Bomfim, Andreas Gerstlauer, "Integration of Virtual Platform Models into a System-Level Design Framework," CERC, UT Austin, Technical Report UT-CERC-10-02, August 2010.
Andreas Gerstlauer, Dongwan Shin, Samar Abdi, Pramod Chandraiah and Daniel D. Gajski, "Design of a MP3 Decoder using the System-On-Chip Environment (SCE)," CECS, UC Irvine, Technical Report CECS-TR-07-05, November 2007.
Eric James Johnson, Andreas Gerstlauer and Rainer Doemer, "Efficient Debugging and Tracing of System Level Designs," CECS, UC Irvine, Technical Report CECS-TR-06-08, May 2006.
Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer and Rainer Dömer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor," CECS, UC Irvine, Technical Report CECS-TR-06-06, May 2006.
Daniel Gajski, Andreas Gerstlauer, Rainer Dömer, Samar Abdi, Jerry Peng and Dongwan Shin, "TL Environment," CECS, UC Irvine, Technical Report CECS-TR-05-10, July 2005.
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Communication Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-25, July 2004.
Dongwan Shin, Lukai Cai, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Transaction-Level Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-24, July 2004.
Dongwan Shin, Junyu Peng, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Network Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-23, July 2004.
Junyu Peng, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Architecture Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-22, July 2004.
Rainer Dömer, Andreas Gerstlauer, and Dongwan Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," CECS, UC Irvine, Technical Report CECS-TR-04-19, July 2004.
Dongwan Shin, Andreas Gerstlauer and Daniel Gajski, "Communication Link Synthesis for SoC," CECS, UC Irvine, Technical Report CECS-TR-04-16, June 2004.
Dongwan Shin, Andreas Gerstlauer and Daniel Gajski, "Network Synthesis for SoC," CECS, UC Irvine, Technical Report CECS-TR-04-15, June 2004.
Lucai Cai, Andreas Gerstlauer, and Daniel Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," CECS, UC Irvine, Technical Report CECS-TR-04-04, October 2003.
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, "C-based Interactive RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-03-42, December 2003.
Samar Abdi, Junyu Peng, Haobo Yu, Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-03-41, July 2003.
Andreas Gerstlauer, "Communication Abstractions for System-Level Design and Synthesis," CECS, UC Irvine, Technical Report CECS-TR-03-30, October 2003.
Andreas Gerstlauer, Kiran Ramineni, Rainer Dömer and Daniel D. Gajski, "System-On-Chip Specification Style Guide," CECS, UC Irvine, Technical Report CECS-TR-03-21, June 2003.
Haobo Yu, Andreas Gerstlauer, Daniel Gajski, "RTOS Scheduling in Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-12, March 2003.
Daniel Gajski, Junyu Peng, Andreas Gerstlauer, Haobo Yu, Dongwan Shin, "System Design Methodology and Tools," CECS, UC Irvine, Technical Report CECS-TR-03-02, January 2003.
S. Abdi, J. Peng, R. Dömer, D. Shin, A. Gerstlauer, A. Gluhak, L.Cai, Q. Xie, H. Yu, P. Zhang, D. Gajski, "System-On-Chip Environment (SCE): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-02-28, September 2002.
Andreas Gerstlauer, Daniel D. Gajski, "System-Level Abstraction Semantics," CECS, UC Irvine, Technical Report CECS-TR-02-17, July 2002.
Andreas Gerstlauer, "SpecC Modeling Guidelines," CECS, UC Irvine, Technical Report CECS-TR-02-16, April 2002.
Junyu Peng, Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, "Interactive System Design Flow," CECS, UC Irvine, Technical Report CECS-TR-02-15, April 2002.
Wolfgang Mueller, Rainer Dömer, Andreas Gerstlauer, "The Formal Execution Semantics of SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-04, January 2002.
Wolfgang Mueller, Rainer Dömer, Andreas Gerstlauer, "The Formal Execution Semantics of SpecC," UC Irvine, Technical Report ICS-TR-01-59, November 2001.
Andreas Gerstlauer, "SpecC Modeling Guidelines," CECS, UC Irvine, Technical Report ICS-TR-00-48, August 2000.
Andreas Gerstlauer, "Communication Software Code Generation," UC Irvine, Technical Report ICS-TR-00-46, August 2000.
D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao, "The SpecC Methodology," UC Irvine, Technical Report ICS-TR-99-56, December 1999.
L. Cai, J. Peng, C. Chang, A. Gerstlauer, H. Li, A. Selka, C. Siska, L. Sun, S. Zhao and D. Gajski, "Design of a JPEG Encoding System," UC Irvine, Technical Report ICS-TR-99-54, November 1999.
Andreas Gerstlauer, Shuqing Zhao, Daniel D. Gajski and Arkady M. Horak, "Design of a GSM Vocoder using SpecC Methodology," UC Irvine, Technical Report ICS-TR-99-11, March 1999.
Andreas Gerstlauer, Shuqing Zhao and Daniel D. Gajski, "VHDL+/SpecC Comparisons - A Case Study," UC Irvine, Technical Report ICS-TR-98-23, May 1998.

Professional Documents

R. Dömer, A. Gerstlauer, D. Gajski, "SpecC Language Reference Manual, Version 2.0," SpecC Technology Open Consortium (STOC), Japan, December 2002.
R. Dömer, A. Gerstlauer, D. Gajski, "SpecC Language Reference Manual, Version 1.0," SpecC Technology Open Consortium (STOC), Japan, March 2001.

Tutorials

A. Gerstlauer, "Principles: Modeling, Synthesis and Verification" in System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs, organized by Daniel D. Gajski, full-day tutorial at Design Automation and Test in Europe (DATE) Conference, Nice, France, April 2009.
A. Gerstlauer, "Embedded System Design: Modeling" in Concepts and Tools for Practical Embedded System Design, organized by Nikil Dutt, half-day tutorial at the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2007.
R. Dömer, A. Gerstlauer, P. Kritzinger, M. Olivarez, "The SpecC System-Level Design Language and Methodology, Part 2," Embedded Systems Conference (ESC), San Francisco, March 2002.
A. Gerstlauer, "System-Level Modeling and Design: Experimentation with SpecC," in System Level Specification beyond RTL, organized by Daniel D. Gajski, half-day tutorial at Design, Automation and Test in Europe (DATE) Conference, Paris, France, March 2002.
A. Gerstlauer, "Modeling and Design with SpecC" and "Design of a GSM Vocoder," in SpecC Language and Design Methodology, organized by Daniel D. Gajski, half-day tutorial at Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, March 2001.
A. Gerstlauer, "Modeling and Design with SpecC," in SpecC Language and Design Methodology, organized by Daniel D. Gajski, full-day tutorial at the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2001.

Theses

A. Gerstlauer, Modeling Flow for Automated System Design and Exploration, Ph.D. Dissertation, Information and Computer Science, University of California, Irvine, 2004.
A. Gerstlauer, Entwicklung einer Zellbibliothek in CMOS und Passtransistorlogik für Low-Power-Anwendungen, Diplomarbeit, Integrierter Systementwurf, Fakultät Informatik, Universität Stuttgart, 1997 [Zusammenfassung].
- A. Gerstlauer, Development of a Standard Cell Library in CMOS and Pass Transistor Logic for Low Power Applications, Diploma/Masters Thesis, Integrated Systems Engineering, Dept. of Computer Science, University of Stuttgart, Germany, 1997 [Abstract].
A. Gerstlauer, VHDL-Entwurf eines Prozessors mit RISC-Architektur, 2. Studienarbeit, Institut für Mikroelektronik Stuttgart, Universität Stuttgart, 1996.
- A. Gerstlauer, Design of a Processor with RISC Architecture in VHDL, Institute for Microelectronics Stuttgart, University of Stuttgart, Germany, 1996 [Abstract].
A. Gerstlauer, Simulation verschiedener Permit-Zuweisungsverfahren in einem ATM-Zugangsnetz, 1. Studienarbeit, Institut für Nachrichtenvermittlung und Datenverarbeitung, Fakultät Elektrotechnik, Universität Stuttgart, 1994.
- A. Gerstlauer, Simulation of Different Permit Allocation Strategies in an ATM Access Network, 1st Semester Project Thesis, Institute of Communication Networks and Computer Engineering, Dept. of Electrical Engineering, University of Stuttgart, Germany, 1994 [Abstract].

List of publications from the previous HIPERLOGIC project.