Romi Datta
Romi Datta received his Ph.D. in
Electrical and Computer Engineering from the University of Texas at Austin in
2006. He held design test and DFT positions in the semiconductor industry,
having worked in IBM Research, IBM’s Cell design center, Texas Instruments and
Nvidia till he decided to go back to schools to pursue an MBA. In 2011 he held a
summer position in Strategic Planning at Intel, where he worked on identifying
and evaluating new business opportunities for Intel in the software and services
space. He has 10 patents issued or pending and over a dozen publications in
areas of design and test of ICs. He has served on the technical program
committee of International Symposium on Quality Electronic Design, International
Symposium on Defect and Fault Tolerant VLSI Systems and International Test
Synthesis Workshop. He was also a member of the Technical Advisory Board
(Computer Aided Design and Test) for Semiconductor Research Consortium, and a
member of the IEEE Standardization Committee for IJTAG.
Gian Gerosa has 29 years of experience in the semiconductor industry since obtaining his PhD in electrical engineering from the Ohio State University (OSU) in 1982. He has a BSEE from the Georgia Institute of Technology (1977) and a MSEE from OSU (1980). He started his career at Intel Corporation as a device engineer in Portland Technology Development working on 1.2um CMOS technology. He moved on to circuit design related activities on various memory product projects at MOTOROLA. In the 90’s, Gian was involved in the design of a family of PowerPC micro-processors in a joint venture with IBM. He led the PowerPC603 integration team where he was responsible for integration, PLL design, clocking, IO buffer design, and ESD protection. Later, he took the role of design manager for the PowerPC750 RISC microprocessor. He re-joined Intel to work on high performance desk-top IA32 microprocessor development in Austin, Texas. Later on, Gian led path-finding and technology readiness efforts for a low power IA core design which eventually became Intel’s 1st ATOM processor product. He managed the L2 cache and analog (PLL, IO, fuses, digital thermal sensing) design teams for the 45nm ATOM products which included a 2nd generation ATOM-cpu-based SoC. Gian just completed (as a member of the design team) a 3rd generation design of a fully integrated ATOM-cpu-based SoC in 32nm. He is currently involved in 32nm and 22nm silicon bring-up activities as a Principal Engineer. Gian has 12 issued patents; he has contributed to over 20 refereed papers related to chip design, circuit design, and ESD protection; 2 are full-length journal papers (JSSC) on the PowerPC 603 and PowerPC 750 RISC microprocessors and a 3rd one on Intel’s 1st ATOM processor. Gian was a member of the ISSCC’s digital sub-committee (1997-1999) where he co-chaired several clocking/logic sessions and was the 1998 JSSC guest editor.
H. Peter Hofstee
holds a Drs. degree in theoretical physics from Groningen University in the Netherlands, and MS and PhD
degrees in computer science from the California Institute of Technology. He is
interested in concurrent systems in general and in high-performance
microprocessor design in particular. From '95 to '01 he worked in the IBM Austin
Research Laboratory on high-performance microprocessor prototypes including the
first 1GHz CMOS microprocessor in '98. He has consulted extensively for the IBM
server division on future microprocessor designs. He is currently microprocessor
architect in the newly formed "Cell" design center, a
collaboration between Sony, Toshiba and IBM.
Mark
McDermott has 35 years of experience in
product development of silicon systems.
Mark is currently a Research Fellow in the ECE Department at the
Univ. of Texas. Prior to this he was VP of Engineering at Coherent Logix, CEO of DynaFlow Computing, Inc., VP Engineering
at Somerset Embedded Technologies, Inc., VP Engineering at VisionFlow, Inc.,
General Manager and Director of the Texas Development Center for Intel
Corporation, Director of the PowerPC Somerset Design Center and Director of the
Austin Design Center for Cyrix, Inc. Mark co-founded Logical Silicon Solutions,
Inc. in 1990, Accelerated Solutions Corp. in 1984 and MonoCom
Systems, Inc. in 1981. Previous hardware
and software design experience includes: low-power CMOS microprocessors, speech
synthesizers, BiCMOS cache controllers, logic simulation hardware accelerators, micro-coded bit-slice processors, traffic
controllers, industrial controllers and communication controllers.
His current interests include research on how to improve design and verification productivity in today’s silicon system designs. He is an Adjunct Assistant Professor in ECE Department at the University of Texas where he teaches graduate level courses in silicon system design and technical entrepreneurship. Mark received a Bachelors degree in Electrical Engineering from the University of New Mexico and a Masters in Electrical Engineering from the University of Texas. Mark is a registered professional engineer and a member of the IEEE, ACM and NSPE/TSPE. He has 19 patents and a number of publications in the areas of IC design and engineering management.
Sankaran
Menon
Dr. Sankaran Menon received his
MSEE degree in 1989 and Ph.D. degree in Electrical and Computer Engineering from
Colorado State University, Fort Collins, Colorado in 1994 in the area of Design
for Testability. He received his undergraduate degree in 1979 and received his
MS (Advanced Electronics) degree from JNTU, Hyderabad,
India in 1986. He has worked at NRSA in India, from 1979 to 1986. He
worked as Assistant Professor with the Electrical and Computer Engineering
Department at the SD school of Mines and Technology, Rapid City, South Dakota
from 1994 to 1997. He then made his transition from academia to Industry and
joined Texas Instruments, and then to Intel Corporation. Presently, he is with
the Intel® Atom TM DFX team working on Design
for Testability and Debug activities at the Texas Design Center of Intel
Corporation, Austin, Texas, working on Intel® Atom
TM CPUs and SoCs. He has also worked on DFT for Intel® DSPs as well as
Xscale (ARM) based SoCs. He has published over 40 papers in various journals and
conferences in the area of Design for Testability. Dr. Menon is member of Tau
Beta Pi, Sigma Xi, Senior Member of the IEEE, and Fellow of IETE, India. He is
very active with IEEE activities, workshops and conferences; he was the Program
Chair and Finance Chair of 2010 IEEE Defect and Data Based Testing (D3T)
workshop. He is Program Committee member of Microprocessor Test & Validation
Workshop, Workshop on Unique Chips and Systems and TTTC Technical Education
Program (TEP).
Binta Patel
Binta has a Master’s degree in electrical engineering from NYU (1991) and a
Bachelors of Engineering in Electronics from Nagpur University, India (1989).
She started her career at IBM working on 90nm CMOS (bulk and SOI) dynamic
circuit topologies, register files, adders and embedded caches for powerPC
processors. In 2000 Binta Joined Intel to work on Intel microprocessor
development in Austin, Texas; she worked on path finding various circuit
topologies for cache, execution and front end logic units. In 2005 she led the
team that developed a low power quad-pumped IO interfaces (Intel's
Front-Side-Bus) for Intel’s first low power processor “ATOM” in 45nm CMOS. In
addition to designing a low power FSB with CMOS signaling, she drove analog
circuits, clock architecture and thermal sensor designs; she drove several low
power circuit schemes (in 45nm) that helped Intel ATOM microprocessors meet
their idle and standby power targets. Currently she is working on 32nm low power
PLL architectures and implementations as well as a new low power digital thermal
sensor for SoC applications. In addition, Binta continues to define integrated
clock architectures for ATOM based SoCs in 32nm and 22nm.
Héctor Sánchez
Héctor Sánchez is a native of San Juan, Puerto Rico. He is the Chief Engineer in charge of the Advanced Circuits Design Center (AC/DC) of the Networking and Computing Systems Group of the Motorola Semiconductor Products Sector, a group dedicated to the development of PLL, I/O, and future technology. Over the last 13 years he has worked as a custom circuit designer with Motorola's Semiconductor Products Sector in Austin, Texas working on the development of PowerPC microprocessors. He received a BS and ME degrees in electrical engineering from Texas A&M University in 1987 and 1990, respectively. His professional activities include: phase-locked loop circuit design, clock generation, clock distribution, high-speed analog-digital circuits, design for low-power, microprocessor thermal management, temperature sensor circuit design, I/O buffer design, microprocessor chip integration, and technology definition for sub-100nm technologies. He has authored more than 17 papers and has 8 patents granted and several pending. He is a member of the Digital sub-committee at the IEEE ISSCC (2001-2004) and a member of the IEEE International SOI Conference Committee ( 2002-2004). He is a member of IEEE.