#----------------------------------------------------------- # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 # Start of session at: Wed May 1 15:22:36 2024 # Process ID: 4050685 # Current directory: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024 # Command line: vivado ultra96v2_oob.xpr # Log file: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/vivado.log # Journal file: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/vivado.jou # Running On: mario.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404275 MB #----------------------------------------------------------- start_gui open_project ultra96v2_oob.xpr WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/jkacines/RAID_PROJECT/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. open_project: Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 7475.078 ; gain = 348.309 ; free physical = 243632 ; free virtual = 344426 update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} Reading block design file ... Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1 Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3 Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1 Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_0 Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9 Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0 Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1 Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1 Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_0 Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_1 Successfully read diagram from block design file update_gui_for_PARAM_VALUE.C_XIP_MODE- xip_mode: 0 spi_mode: 0 xip_perf_mode: 1 update_gui_for_PARAM_VALUE.C_XIP_PERF_MODE- xip_mode: 0 xip_perf_mode: 1 axi4_interface: 0 startgroup set_property CONFIG.C_NUM_TRANSFER_BITS {8} [get_bd_cells axi_quad_spi_0] endgroup update_gui_for_PARAM_VALUE.C_XIP_MODE- xip_mode: 0 spi_mode: 0 xip_perf_mode: 1 update_gui_for_PARAM_VALUE.C_XIP_PERF_MODE- xip_mode: 0 xip_perf_mode: 1 axi4_interface: 0 startgroup set_property CONFIG.C_NUM_TRANSFER_BITS {8} [get_bd_cells axi_quad_spi_1] endgroup save_bd_design Wrote : Wrote : reset_run synth_1 reset_run ultra96v2_oob_axi_quad_spi_0_0_synth_1 reset_run ultra96v2_oob_axi_quad_spi_0_1_synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 64 INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_0 ############################################################################## INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are are asynchronous. ############################################################################## INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_1 ############################################################################## INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are are asynchronous. ############################################################################## WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /BRAM/axi_bram_ctrl_1/S_AXI(0) and /smartconnect_1/M11_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /BRAM/axi_bram_ctrl_1/S_AXI(0) and /smartconnect_1/M11_AXI(16) Wrote : WARNING: [BD 41-2384] Width mismatch when connecting pin: '/BRAM/blk_mem_gen_1/addra'(32) to pin: '/BRAM/axi_bram_ctrl_0/bram_addr_a'(13) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/BRAM/blk_mem_gen_1/addrb'(32) to pin: '/BRAM/axi_bram_ctrl_1/bram_addr_a'(13) - Only lower order bits will be connected. Verilog Output written to : /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v WARNING: [BD 41-2384] Width mismatch when connecting pin: '/BRAM/blk_mem_gen_1/addra'(32) to pin: '/BRAM/axi_bram_ctrl_0/bram_addr_a'(13) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/BRAM/blk_mem_gen_1/addrb'(32) to pin: '/BRAM/axi_bram_ctrl_1/bram_addr_a'(13) - Only lower order bits will be connected. Verilog Output written to : /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_quad_spi_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_quad_spi_1 . Exporting to file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_axi_quad_spi_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_axi_quad_spi_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork() INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_axi_quad_spi_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_axi_quad_spi_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry bc014819dce43494 to dir: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/c/bc014819dce43494/ultra96v2_oob_smartconnect_1_0.dcp to /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/c/bc014819dce43494/ultra96v2_oob_smartconnect_1_0_stub.v to /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/c/bc014819dce43494/ultra96v2_oob_smartconnect_1_0_stub.vhdl to /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/c/bc014819dce43494/ultra96v2_oob_smartconnect_1_0_sim_netlist.v to /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/c/bc014819dce43494/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl to /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_1_0, cache-ID = bc014819dce43494; cache size = 3163.852 MB. config_ip_cache: Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 8171.062 ; gain = 184.605 ; free physical = 243262 ; free virtual = 344001 [Wed May 1 15:26:04 2024] Launched ultra96v2_oob_axi_quad_spi_0_0_synth_1, ultra96v2_oob_axi_quad_spi_0_1_synth_1, synth_1... Run output will be captured here: ultra96v2_oob_axi_quad_spi_0_0_synth_1: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_axi_quad_spi_0_0_synth_1/runme.log ultra96v2_oob_axi_quad_spi_0_1_synth_1: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_axi_quad_spi_0_1_synth_1/runme.log synth_1: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log [Wed May 1 15:26:04 2024] Launched impl_1... Run output will be captured here: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs: Time (s): cpu = 00:01:25 ; elapsed = 00:01:29 . Memory (MB): peak = 8562.164 ; gain = 575.707 ; free physical = 243251 ; free virtual = 343967 write_hw_platform -fixed -force -file /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob_wrapper.xsa INFO: [Project 1-1918] Creating Hardware Platform: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob_wrapper.xsa ... INFO: [Project 1-1943] The Hardware Platform can be used for Hardware INFO: [Project 1-1941] Successfully created Hardware Platform: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob_wrapper.xsa INFO: [Hsi 55-2053] elapsed time for repository (/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/embeddedsw) loading 0 seconds write_hw_platform: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 8562.164 ; gain = 0.000 ; free physical = 243213 ; free virtual = 344023 exit INFO: [Common 17-206] Exiting Vivado at Wed May 1 15:40:42 2024...