#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Thu May  2 22:32:04 2024
# Process ID: 446940
# Current directory: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024
# Command line: vivado ultra96v2_oob.xpr
# Log file: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/vivado.log
# Journal file: /misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/vivado.jou
# Running On: mario.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404275 MB
#-----------------------------------------------------------
start_gui
open_project ultra96v2_oob.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/jkacines/RAID_PROJECT/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
open_project: Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 7472.398 ; gain = 374.188 ; free physical = 356268 ; free virtual = 372779
update_compile_order -fileset sources_1
open_bd_design {/misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd}
Reading block design file </misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd>...
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3
Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2
Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0
Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1
Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_0
Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_1
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0
Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_0
Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - axi_quad_spi_1
Successfully read diagram <ultra96v2_oob> from block design file </misc/scratch/jkacines/RAID_PROJECT/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd>
update_gui_for_PARAM_VALUE.C_XIP_MODE- xip_mode: 0 spi_mode: 0 xip_perf_mode: 1
update_gui_for_PARAM_VALUE.C_XIP_PERF_MODE- xip_mode: 0 xip_perf_mode: 1 axi4_interface: 0
exit
INFO: [Common 17-206] Exiting Vivado at Thu May  2 22:34:11 2024...