#----------------------------------------------------------- # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 # Start of session at: Thu May 2 21:27:41 2024 # Process ID: 114798 # Current directory: /misc/scratch/ibansal/project/SHA3_2022.2 # Command line: vivado ultra96v2_oob.xpr # Log file: /misc/scratch/ibansal/project/SHA3_2022.2/vivado.log # Journal file: /misc/scratch/ibansal/project/SHA3_2022.2/vivado.jou # Running On: mario.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404275 MB #----------------------------------------------------------- start_gui WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project ultra96v2_oob.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ibansal/project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. open_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 7407.871 ; gain = 262.430 ; free physical = 359209 ; free virtual = 375299 update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} Reading block design file ... Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3 Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1 Adding component instance block -- user.org:user:PWM_w_Int:1.0 - PWM_w_Int_1 Adding component instance block -- user.org:user:PWM_w_Int:1.0 - PWM_w_Int_0 Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1 Adding component instance block -- ecelrc:user:Capture_Timer:1.0 - Capture_Timer_0 Adding component instance block -- ecelrc:user:SHA3_BURST_MASTER:1.0 - SHA3_BURST_MASTER_0 Successfully read diagram from block design file INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change WARNING: [IP_Flow 19-474] Invalid Parameter 'Component_Name' INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change startgroup set_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {3} [get_bd_cells zynq_ultra_ps_e_0] INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change endgroup save_bd_design Wrote : reset_run synth_1 WARNING: [Vivado 12-1017] Problems encountered: 1. Failed to delete one or more files in run directory /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.runs/synth_1 reset_run ultra96v2_oob_zynq_ultra_ps_e_0_0_synth_1 WARNING: [Vivado 12-1017] Problems encountered: 1. Failed to delete one or more files in run directory /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.runs/ultra96v2_oob_zynq_ultra_ps_e_0_0_synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 32 CRITICAL WARNING: [BD 17-146] Maximum Supported frequency for /zynq_ultra_ps_e_0/maxihpm0_fpd_aclk is 333.333 CRITICAL WARNING: [BD 17-146] Maximum Supported frequency for /zynq_ultra_ps_e_0/maxihpm1_fpd_aclk is 333.333 CRITICAL WARNING: [BD 17-146] Maximum Supported frequency for /zynq_ultra_ps_e_0/saxi_lpd_aclk is 333.333 INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change ERROR: [IP_Flow 19-3488] Validation failed for parameter 'AXI CLK Frequency(C_S_AXI_ACLK_FREQ_HZ_d)' for BD Cell 'ULTRA96_IO/Low_Speed_MEZZ/axi_uart16550_0'. Value '500.0' is out of the range (25.0,300.0) INFO: [IP_Flow 19-3438] Customization errors found on 'ULTRA96_IO/Low_Speed_MEZZ/axi_uart16550_0'. Restoring to previous valid configuration. ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ERROR: [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ::xilinx.com_ip_axi_uart16550_2.0::post_propagate Line 13 ERROR: [IP_Flow 19-3488] Validation failed for parameter 'AXI CLK Frequency(C_S_AXI_ACLK_FREQ_HZ_d)' for BD Cell 'ULTRA96_IO/Low_Speed_MEZZ/axi_uart16550_1'. Value '500.0' is out of the range (25.0,300.0) INFO: [IP_Flow 19-3438] Customization errors found on 'ULTRA96_IO/Low_Speed_MEZZ/axi_uart16550_1'. Restoring to previous valid configuration. ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ERROR: [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ::xilinx.com_ip_axi_uart16550_2.0::post_propagate Line 13 ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_rst_ps8_0_100M_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_zynq_ultra_ps_e_0_0 INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork() INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_rst_ps8_0_100M_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_zynq_ultra_ps_e_0_0 ERROR: [Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution. exit INFO: [Common 17-206] Exiting Vivado at Thu May 2 21:38:32 2024...