#----------------------------------------------------------- # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 # Start of session at: Thu May 2 23:55:59 2024 # Process ID: 747825 # Current directory: /misc/scratch/ibansal/project/SHA3_2022.2 # Command line: vivado ultra96v2_oob.xpr # Log file: /misc/scratch/ibansal/project/SHA3_2022.2/vivado.log # Journal file: /misc/scratch/ibansal/project/SHA3_2022.2/vivado.jou # Running On: mario.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404275 MB #----------------------------------------------------------- start_gui WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project ultra96v2_oob.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ibansal/project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. open_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 7409.770 ; gain = 258.227 ; free physical = 362737 ; free virtual = 379405 update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} Reading block design file ... Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3 Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1 Adding component instance block -- user.org:user:PWM_w_Int:1.0 - PWM_w_Int_1 Adding component instance block -- user.org:user:PWM_w_Int:1.0 - PWM_w_Int_0 Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1 Adding component instance block -- ecelrc:user:Capture_Timer:1.0 - Capture_Timer_0 Adding component instance block -- ecelrc:user:SHA3_BURST_MASTER:1.0 - SHA3_BURST_MASTER_0 Successfully read diagram from block design file ipx::edit_ip_in_project -upgrade true -name SHA3_BURST_MASTER_v1_0_project -directory /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.tmp/SHA3_BURST_MASTER_v1_0_project /misc/scratch/ibansal/project/ip_repo/SHA3_BURST_MASTER_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available create_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 7950.691 ; gain = 0.000 ; free physical = 362597 ; free virtual = 379266 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ibansal/project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data ipx::edit_ip_in_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 7950.691 ; gain = 0.000 ; free physical = 362599 ; free virtual = 379268 update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ibansal/project/ip_repo/SHA3_BURST_MASTER_1_0/component.xml' ignored by IP packager. ipx::update_checksums [ipx::current_core] ipx::save_core [ipx::current_core] set_property core_revision 69 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] set_property core_revision 70 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] current_project ultra96v2_oob update_ip_catalog -rebuild -scan_changes INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ibansal/project/ip_repo'. report_ip_status -name ip_status current_project SHA3_BURST_MASTER_v1_0_project ERROR: [BD 5-104] A block design must be open to run this command. Please create/open a block design. ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors. ERROR: [BD 41-1273] Error running can_apply_rule TCL procedure: ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors. ::xilinx.com_bd_rule_sys_mgmt_wiz::can_apply_rule Line 4 current_project ultra96v2_oob upgrade_ip -vlnv ecelrc:user:SHA3_BURST_MASTER:1.0 [get_ips ultra96v2_oob_SHA3_BURST_MASTER_0_3] -log ip_upgrade.log Upgrading '/misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_SHA3_BURST_MASTER_0_3 (SHA3_BURST_MASTER_v1.0 1.0) from revision 68 to revision 70 Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ibansal/project/SHA3_2022.2/ip_upgrade.log'. upgrade_ip: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 7950.691 ; gain = 0.000 ; free physical = 362758 ; free virtual = 379453 export_ip_user_files -of_objects [get_ips ultra96v2_oob_SHA3_BURST_MASTER_0_3] -no_script -sync -force -quiet reset_run synth_1 launch_runs impl_1 -to_step write_bitstream -jobs 32 INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in Low-Area Mode. WARNING: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: IP ultra96v2_oob_smartconnect_1_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S00_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received. WARNING: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: IP ultra96v2_oob_smartconnect_1_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S01_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received. WARNING: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: If WRAP transactions are required then turn off Low-area mode using ADVANCED_PROPERTIES. Execute following: set_property CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {disable_low_area_mode 1}} [get_bd_cells /ultra96v2_oob_smartconnect_1_0] WARNING: [BD 41-237] Bus Interface property WUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /SHA3_BURST_MASTER_0/M00_AXI(1) WARNING: [BD 41-237] Bus Interface property RUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /SHA3_BURST_MASTER_0/M00_AXI(1) WARNING: [BD 41-237] Bus Interface property BUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /SHA3_BURST_MASTER_0/M00_AXI(1) WARNING: [BD 41-927] Following properties on pin /ULTRA96_IO/SYS_MGMT/system_management_wiz_0/s_axi_aclk have been updated from connected ip, but BD cell '/ULTRA96_IO/SYS_MGMT/system_management_wiz_0' does not accept parameter changes, so they may not be synchronized with cell properties: FREQ_HZ = 150000000 Please resolve any mismatches by directly setting properties on BD cell to completely resolve these warnings. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. WARNING: [BD 41-2671] The dangling interface net will not be written out to the BD file. Wrote : WARNING: [BD 41-2384] Width mismatch when connecting pin: '/SHA3_BURST_MASTER_0/m00_axi_rid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_awid'(6) to pin: '/SHA3_BURST_MASTER_0/m00_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_arid'(6) to pin: '/SHA3_BURST_MASTER_0/m00_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/SHA3_BURST_MASTER_0/m00_axi_bid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected. Verilog Output written to : /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v WARNING: [BD 41-2384] Width mismatch when connecting pin: '/SHA3_BURST_MASTER_0/m00_axi_rid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_awid'(6) to pin: '/SHA3_BURST_MASTER_0/m00_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/zynq_ultra_ps_e_0/saxigp6_arid'(6) to pin: '/SHA3_BURST_MASTER_0/m00_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/SHA3_BURST_MASTER_0/m00_axi_bid'(1) to pin: '/zynq_ultra_ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected. Verilog Output written to : /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_ar_node/s_sc_payld'(181) to pin: '/s00_nodes/S_SC_AR_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_aw_node/s_sc_payld'(181) to pin: '/s00_nodes/S_SC_AW_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_nodes/s01_ar_node/s_sc_payld'(181) to pin: '/s01_nodes/S_SC_AR_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_nodes/s01_aw_node/s_sc_payld'(181) to pin: '/s01_nodes/S_SC_AW_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_nodes/m00_r_node/s_sc_payld'(58) to pin: '/m00_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_nodes/m00_b_node/s_sc_payld'(12) to pin: '/m00_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_nodes/m01_r_node/s_sc_payld'(58) to pin: '/m01_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_nodes/m01_b_node/s_sc_payld'(12) to pin: '/m01_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_nodes/m02_r_node/s_sc_payld'(58) to pin: '/m02_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_nodes/m02_b_node/s_sc_payld'(12) to pin: '/m02_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_nodes/m03_r_node/s_sc_payld'(58) to pin: '/m03_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_nodes/m03_b_node/s_sc_payld'(12) to pin: '/m03_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_nodes/m04_r_node/s_sc_payld'(58) to pin: '/m04_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_nodes/m04_b_node/s_sc_payld'(12) to pin: '/m04_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_nodes/m05_r_node/s_sc_payld'(58) to pin: '/m05_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_nodes/m05_b_node/s_sc_payld'(12) to pin: '/m05_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_nodes/m06_r_node/s_sc_payld'(58) to pin: '/m06_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_nodes/m06_b_node/s_sc_payld'(12) to pin: '/m06_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_nodes/m07_r_node/s_sc_payld'(58) to pin: '/m07_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_nodes/m07_b_node/s_sc_payld'(12) to pin: '/m07_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_nodes/m08_r_node/s_sc_payld'(58) to pin: '/m08_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_nodes/m08_b_node/s_sc_payld'(12) to pin: '/m08_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_nodes/m09_r_node/s_sc_payld'(58) to pin: '/m09_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_nodes/m09_b_node/s_sc_payld'(12) to pin: '/m09_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_nodes/m10_r_node/s_sc_payld'(58) to pin: '/m10_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_nodes/m10_b_node/s_sc_payld'(12) to pin: '/m10_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_axi2sc/s_sc_r_payld'(56) to pin: '/s00_nodes/M_SC_R_payld'(58) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_axi2sc/s_sc_b_payld'(10) to pin: '/s00_nodes/M_SC_B_payld'(12) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_axi2sc/s_sc_r_payld'(56) to pin: '/s01_nodes/M_SC_R_payld'(58) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_axi2sc/s_sc_b_payld'(10) to pin: '/s01_nodes/M_SC_B_payld'(12) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_ar_payld'(177) to pin: '/m00_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_aw_payld'(177) to pin: '/m00_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_ar_payld'(177) to pin: '/m01_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_aw_payld'(177) to pin: '/m01_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_ar_payld'(177) to pin: '/m02_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_aw_payld'(177) to pin: '/m02_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_ar_payld'(177) to pin: '/m03_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_aw_payld'(177) to pin: '/m03_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_ar_payld'(177) to pin: '/m04_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_aw_payld'(177) to pin: '/m04_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_ar_payld'(177) to pin: '/m05_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_sc2axi/s_sc_aw_payld'(177) to pin: '/m05_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_ar_payld'(177) to pin: '/m06_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_sc2axi/s_sc_aw_payld'(177) to pin: '/m06_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_ar_payld'(177) to pin: '/m07_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_sc2axi/s_sc_aw_payld'(177) to pin: '/m07_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_ar_payld'(177) to pin: '/m08_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_sc2axi/s_sc_aw_payld'(177) to pin: '/m08_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_ar_payld'(177) to pin: '/m09_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_sc2axi/s_sc_aw_payld'(177) to pin: '/m09_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_ar_payld'(177) to pin: '/m10_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_sc2axi/s_sc_aw_payld'(177) to pin: '/m10_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_ar_node/s_sc_payld'(181) to pin: '/s00_nodes/S_SC_AR_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_nodes/s00_aw_node/s_sc_payld'(181) to pin: '/s00_nodes/S_SC_AW_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_nodes/s01_ar_node/s_sc_payld'(181) to pin: '/s01_nodes/S_SC_AR_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_nodes/s01_aw_node/s_sc_payld'(181) to pin: '/s01_nodes/S_SC_AW_payld'(177) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_nodes/m00_r_node/s_sc_payld'(58) to pin: '/m00_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_nodes/m00_b_node/s_sc_payld'(12) to pin: '/m00_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_nodes/m01_r_node/s_sc_payld'(58) to pin: '/m01_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_nodes/m01_b_node/s_sc_payld'(12) to pin: '/m01_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_nodes/m02_r_node/s_sc_payld'(58) to pin: '/m02_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_nodes/m02_b_node/s_sc_payld'(12) to pin: '/m02_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_nodes/m03_r_node/s_sc_payld'(58) to pin: '/m03_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_nodes/m03_b_node/s_sc_payld'(12) to pin: '/m03_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_nodes/m04_r_node/s_sc_payld'(58) to pin: '/m04_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_nodes/m04_b_node/s_sc_payld'(12) to pin: '/m04_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_nodes/m05_r_node/s_sc_payld'(58) to pin: '/m05_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m05_nodes/m05_b_node/s_sc_payld'(12) to pin: '/m05_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_nodes/m06_r_node/s_sc_payld'(58) to pin: '/m06_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m06_nodes/m06_b_node/s_sc_payld'(12) to pin: '/m06_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_nodes/m07_r_node/s_sc_payld'(58) to pin: '/m07_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m07_nodes/m07_b_node/s_sc_payld'(12) to pin: '/m07_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_nodes/m08_r_node/s_sc_payld'(58) to pin: '/m08_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m08_nodes/m08_b_node/s_sc_payld'(12) to pin: '/m08_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_nodes/m09_r_node/s_sc_payld'(58) to pin: '/m09_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m09_nodes/m09_b_node/s_sc_payld'(12) to pin: '/m09_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_nodes/m10_r_node/s_sc_payld'(58) to pin: '/m10_nodes/S_SC_R_payld'(56) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m10_nodes/m10_b_node/s_sc_payld'(12) to pin: '/m10_nodes/S_SC_B_payld'(10) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_axi2sc/s_sc_r_payld'(56) to pin: '/s00_nodes/M_SC_R_payld'(58) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s00_axi2sc/s_sc_b_payld'(10) to pin: '/s00_nodes/M_SC_B_payld'(12) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_axi2sc/s_sc_r_payld'(56) to pin: '/s01_nodes/M_SC_R_payld'(58) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/s01_axi2sc/s_sc_b_payld'(10) to pin: '/s01_nodes/M_SC_B_payld'(12) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_ar_payld'(177) to pin: '/m00_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m00_sc2axi/s_sc_aw_payld'(177) to pin: '/m00_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_ar_payld'(177) to pin: '/m01_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m01_sc2axi/s_sc_aw_payld'(177) to pin: '/m01_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_ar_payld'(177) to pin: '/m02_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m02_sc2axi/s_sc_aw_payld'(177) to pin: '/m02_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_ar_payld'(177) to pin: '/m03_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m03_sc2axi/s_sc_aw_payld'(177) to pin: '/m03_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_ar_payld'(177) to pin: '/m04_nodes/M_SC_AR_payld'(181) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/m04_sc2axi/s_sc_aw_payld'(177) to pin: '/m04_nodes/M_SC_AW_payld'(181) - Only lower order bits will be connected. INFO: [Common 17-14] Message 'BD 41-2384' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Exporting to file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block SHA3_BURST_MASTER_0 . Exporting to file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_SHA3_BURST_MASTER_0_3 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork() INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_SHA3_BURST_MASTER_0_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 05d48bcebdd2859a to dir: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.cache/ip/2022.2/0/5/05d48bcebdd2859a/ultra96v2_oob_smartconnect_1_0.dcp to /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.cache/ip/2022.2/0/5/05d48bcebdd2859a/ultra96v2_oob_smartconnect_1_0_stub.v to /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.cache/ip/2022.2/0/5/05d48bcebdd2859a/ultra96v2_oob_smartconnect_1_0_stub.vhdl to /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.cache/ip/2022.2/0/5/05d48bcebdd2859a/ultra96v2_oob_smartconnect_1_0_sim_netlist.v to /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.cache/ip/2022.2/0/5/05d48bcebdd2859a/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl to /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_1_0, cache-ID = 05d48bcebdd2859a; cache size = 2372.226 MB. [Fri May 3 00:22:02 2024] Launched ultra96v2_oob_SHA3_BURST_MASTER_0_3_synth_1, synth_1... Run output will be captured here: ultra96v2_oob_SHA3_BURST_MASTER_0_3_synth_1: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.runs/ultra96v2_oob_SHA3_BURST_MASTER_0_3_synth_1/runme.log synth_1: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.runs/synth_1/runme.log [Fri May 3 00:22:02 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ibansal/project/SHA3_2022.2/ultra96v2_oob.runs/impl_1/runme.log launch_runs: Time (s): cpu = 00:00:58 ; elapsed = 00:01:06 . Memory (MB): peak = 8504.516 ; gain = 319.082 ; free physical = 362453 ; free virtual = 379098