#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Tue Apr 30 21:39:18 2024
# Process ID: 1369462
# Current directory: /misc/scratch/mc76777/mcu_proj
# Command line: vivado
# Log file: /misc/scratch/mc76777/mcu_proj/vivado.log
# Journal file: /misc/scratch/mc76777/mcu_proj/vivado.jou
# Running On: toad.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404276 MB
#-----------------------------------------------------------
start_gui
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
open_project /home/ecelrc/students/mc76777/mont_expo/mont_expo.xpr
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/ecelrc/students/mc76777/mont_expo/mont_expo.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation 
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'mont_expo_test' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj mont_expo_test_vlog.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "mont_expo_test_behav -key {Behavioral:sim_1:Functional:mont_expo_test} -tclbatch {mont_expo_test.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source mont_expo_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'mont_expo_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 7359.031 ; gain = 59.211 ; free physical = 295477 ; free virtual = 372588
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'mont_expo_test' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj mont_expo_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/ecelrc/students/mc76777/mont_expo/mont_expo.srcs/sources_1/new/mont_expo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mont_expo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/ecelrc/students/mc76777/mont_expo/mont_expo.srcs/sources_1/new/mont_mult_modif.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mont_mult_modif
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/ecelrc/students/mc76777/mont_expo/mont_expo.srcs/sim_1/new/tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mont_expo_test
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.mont_mult_modif_default
Compiling module xil_defaultlib.mont_expo_default
Compiling module xil_defaultlib.mont_expo_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot mont_expo_test_behav
execute_script: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 7418.340 ; gain = 0.000 ; free physical = 295419 ; free virtual = 372539
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 7418.340 ; gain = 0.000 ; free physical = 295419 ; free virtual = 372539
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 7418.340 ; gain = 0.000 ; free physical = 295422 ; free virtual = 372534
run all
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj mont_expo_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/ecelrc/students/mc76777/mont_expo/mont_expo.srcs/sources_1/new/mont_expo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mont_expo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/ecelrc/students/mc76777/mont_expo/mont_expo.srcs/sources_1/new/mont_mult_modif.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mont_mult_modif
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/ecelrc/students/mc76777/mont_expo/mont_expo.srcs/sim_1/new/tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mont_expo_test
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.mont_mult_modif_default
Compiling module xil_defaultlib.mont_expo_default
Compiling module xil_defaultlib.mont_expo_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot mont_expo_test_behav
execute_script: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 7418.340 ; gain = 0.000 ; free physical = 295386 ; free virtual = 372507
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 7418.340 ; gain = 0.000 ; free physical = 295386 ; free virtual = 372507
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 7423.109 ; gain = 4.770 ; free physical = 295394 ; free virtual = 372506
run all
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/mont_expo_test/instance_name/count}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/mont_expo_test/instance_name/current_state}} 
relaunch_sim
Command: launch_simulation -step compile -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj mont_expo_test_vlog.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
INFO: [Vivado 12-12493] Simulation top is 'mont_expo_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/ecelrc/students/mc76777/mont_expo/mont_expo.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot mont_expo_test_behav xil_defaultlib.mont_expo_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 7427.117 ; gain = 0.000 ; free physical = 295381 ; free virtual = 372493
run all