#----------------------------------------------------------- # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 # Start of session at: Fri May 3 09:04:12 2024 # Process ID: 1568471 # Current directory: /misc/scratch/ahermez/Final_Project # Command line: vivado # Log file: /misc/scratch/ahermez/Final_Project/vivado.log # Journal file: /misc/scratch/ahermez/Final_Project/vivado.jou # Running On: kamek.ece.utexas.edu, OS: Linux, CPU Frequency: 2977.804 MHz, CPU Physical cores: 32, Host memory: 404276 MB #----------------------------------------------------------- start_gui WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 7366.113 ; gain = 231.434 ; free physical = 366695 ; free virtual = 380075 update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} Reading block design file ... Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0 Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0 Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1 Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3 Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1 Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_0 Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9 Adding component instance block -- ecelrc:user:force_sm:1.0 - force_sm_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_1 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_2 Adding component instance block -- ecelrc:user:application_to_accel:1.0 - application_to_accel_0 Successfully read diagram from block design file startgroup create_bd_cell -type ip -vlnv ecelrc:user:application_to_accel:1.0 application_to_accel_1 WARNING: [IP_Flow 19-2162] IP 'ultra96v2_oob_application_to_accel_1_0' is locked: * IP definition 'application_to_accel_v1.0 (1.0)' for IP 'ultra96v2_oob_application_to_accel_1_0' (customized with software release 2022.2) has a different revision in the IP Catalog. endgroup delete_bd_objs [get_bd_intf_nets everything_except_the_accelerator_M00_AXI] [get_bd_nets Net] [get_bd_cells application_to_accel_0] set_property location {1.5 114 17} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/s00_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_1/s00_axi_aresetn] [get_bd_pins force_sm_0/aresetn] connect_bd_net [get_bd_pins application_to_accel_1/s00_axi_aresetn] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/C_AXIS] [get_bd_intf_pins force_sm_0/const_axis] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/S00_AXI] -boundary_type upper [get_bd_intf_pins everything_except_the_accelerator/M00_AXI] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_2x1_Mux:1.0 AXIS_2x1_Mux_0 endgroup delete_bd_objs [get_bd_cells AXIS_2x1_Mux_0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0 endgroup copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] set_property location {2 356 321} [get_bd_cells Crossbar_Bypass_1x2_1] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] set_property location {2 354 -50} [get_bd_cells Crossbar_Bypass_1x2_0] set_property location {2 353 50} [get_bd_cells Crossbar_Bypass_1x2_1] set_property location {2 366 153} [get_bd_cells Crossbar_Bypass_1x2_2] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/X_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/Y_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_1/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/Z_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_2/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/VX_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_3/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/VY_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_4/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/VZ_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_5/S00_AXIS] group_bd_cells input_data_splitter [get_bd_cells Crossbar_Bypass_1x2_0] [get_bd_cells Crossbar_Bypass_1x2_1] [get_bd_cells Crossbar_Bypass_1x2_2] [get_bd_cells Crossbar_Bypass_1x2_3] [get_bd_cells Crossbar_Bypass_1x2_4] [get_bd_cells Crossbar_Bypass_1x2_5] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_6x1_Mux:1.0 AXIS_6x1_Mux_0 endgroup set_property location {3 981 322} [get_bd_cells AXIS_6x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S05_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S04_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S03_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S00_AXIS] delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn5] delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn6] delete_bd_objs [get_bd_intf_nets input_data_splitter_M01_AXIS] delete_bd_objs [get_bd_intf_nets input_data_splitter_M00_AXIS] delete_bd_objs [get_bd_intf_nets input_data_splitter_M01_AXIS4] delete_bd_objs [get_bd_intf_nets input_data_splitter_M01_AXIS3] delete_bd_objs [get_bd_intf_nets input_data_splitter_M01_AXIS2] delete_bd_objs [get_bd_intf_nets input_data_splitter_M01_AXIS1] delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn1] delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn2] delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn3] delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn4] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S03_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S04_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S05_AXIS] delete_bd_objs [get_bd_intf_pins input_data_splitter/M01_AXIS] delete_bd_objs [get_bd_intf_pins input_data_splitter/M01_AXIS1] delete_bd_objs [get_bd_intf_pins input_data_splitter/M01_AXIS2] delete_bd_objs [get_bd_intf_pins input_data_splitter/M01_AXIS3] delete_bd_objs [get_bd_intf_pins input_data_splitter/M00_AXIS] delete_bd_objs [get_bd_intf_pins input_data_splitter/M01_AXIS4] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Cascaded_FlipFlops:1.0 Cascaded_FlipFlops_0 endgroup connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/x_new_axis] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/y_new_axis] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/z_new_axis] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vx_new_axis] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vy_new_axis] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vz_new_axis] connect_bd_net [get_bd_pins Cascaded_FlipFlops_0/clk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins Cascaded_FlipFlops_0/aresetn] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/X_AXIS] [get_bd_intf_pins force_sm_0/x_axis] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/Y_AXIS] [get_bd_intf_pins force_sm_0/y_axis] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/Z_AXIS] [get_bd_intf_pins force_sm_0/z_axis] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_3x1_Mux:1.0 AXIS_3x1_Mux_0 endgroup set_property location {4 1512 147} [get_bd_cells AXIS_3x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/VX_AXIS] [get_bd_intf_pins AXIS_3x1_Mux_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/VY_AXIS] [get_bd_intf_pins AXIS_3x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/VZ_AXIS] [get_bd_intf_pins AXIS_3x1_Mux_0/S02_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_2x1_Mux:1.0 AXIS_2x1_Mux_0 endgroup set_property location {5 1984 93} [get_bd_cells AXIS_2x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Mux_0/M00_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins force_sm_0/RESULT_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_0/S01_AXIS] startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_3 endgroup set_property -dict [list \ CONFIG.C_Latency {9} \ CONFIG.C_Mult_Usage {Medium_Usage} \ CONFIG.C_Rate {1} \ CONFIG.C_Result_Exponent_Width {8} \ CONFIG.C_Result_Fraction_Width {24} \ CONFIG.Has_RESULT_TREADY {true} \ CONFIG.Maximum_Latency {false} \ CONFIG.Operation_Type {Multiply} \ CONFIG.Result_Precision_Type {Single} \ ] [get_bd_cells floating_point_3] connect_bd_intf_net [get_bd_intf_pins AXIS_2x1_Mux_0/M00_AXIS] [get_bd_intf_pins floating_point_3/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins application_to_accel_1/DT_AXIS] [get_bd_intf_pins floating_point_3/S_AXIS_A] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0 endgroup connect_bd_intf_net [get_bd_intf_pins floating_point_3/M_AXIS_RESULT] [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Fused_2x1Mux_Op:1.0 Fused_2x1Mux_Op_0 endgroup copy_bd_objs / [get_bd_cells {Fused_2x1Mux_Op_0}] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M00_AXIS] [get_bd_intf_pins Fused_2x1Mux_Op_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins Fused_2x1Mux_Op_1/S00_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_1 endgroup connect_bd_intf_net [get_bd_intf_pins Fused_2x1Mux_Op_0/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_1/S00_AXIS] startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_4 endgroup set_property -dict [list \ CONFIG.Add_Sub_Value {Add} \ CONFIG.C_Latency {1} \ CONFIG.Maximum_Latency {false} \ ] [get_bd_cells floating_point_4] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M00_AXIS] [get_bd_intf_pins floating_point_4/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/M00_AXIS] [get_bd_intf_pins floating_point_4/S_AXIS_A] connect_bd_net [get_bd_pins floating_point_4/aclk] [get_bd_pins floating_point_3/aclk] connect_bd_net [get_bd_pins floating_point_3/aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_2x1_Mux:1.0 AXIS_2x1_Mux_1 endgroup set_property location {8 3043 -418} [get_bd_cells AXIS_2x1_Mux_1] connect_bd_intf_net [get_bd_intf_pins floating_point_4/M_AXIS_RESULT] [get_bd_intf_pins AXIS_2x1_Mux_1/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_1/S00_AXIS] group_bd_cells Fused_Adder_2x1Mux [get_bd_cells AXIS_2x1_Mux_1] [get_bd_cells floating_point_4] [get_bd_cells Crossbar_Bypass_1x2_1] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_3x1_Mux:1.0 AXIS_3x1_Mux_1 endgroup copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_1}] set_property location {8 3248 -2} [get_bd_cells AXIS_3x1_Mux_2] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_1}] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_1}] set_property location {8 3241 280} [get_bd_cells AXIS_3x1_Mux_4] set_property location {8 3241 -163} [get_bd_cells AXIS_3x1_Mux_2] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_1}] set_property location {8 3302 495} [get_bd_cells AXIS_3x1_Mux_5] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_1}] set_property location {8 3265 595} [get_bd_cells AXIS_3x1_Mux_6] group_bd_cells Muxes3x1 [get_bd_cells AXIS_3x1_Mux_5] [get_bd_cells AXIS_3x1_Mux_1] [get_bd_cells AXIS_3x1_Mux_2] [get_bd_cells AXIS_3x1_Mux_3] [get_bd_cells AXIS_3x1_Mux_4] [get_bd_cells AXIS_3x1_Mux_6] set_property location {8 3163 -343} [get_bd_cells Muxes3x1] set_property location {3 924 -608} [get_bd_cells Muxes3x1] delete_bd_objs [get_bd_intf_nets input_data_splitter_M00_AXIS] delete_bd_objs [get_bd_intf_nets input_data_splitter_M00_AXIS1] undo INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_intf_nets input_data_splitter_M00_AXIS1]' undo INFO: [Common 17-17] undo 'delete_bd_objs [get_bd_intf_nets input_data_splitter_M00_AXIS]' startgroup delete_bd_objs [get_bd_intf_nets input_data_splitter/Conn10] [get_bd_intf_nets input_data_splitter_M00_AXIS] [get_bd_intf_nets input_data_splitter/Conn11] [get_bd_intf_nets input_data_splitter/Conn12] [get_bd_intf_nets input_data_splitter_M00_AXIS1] [get_bd_intf_nets input_data_splitter_M00_AXIS2] [get_bd_intf_nets input_data_splitter_M00_AXIS3] [get_bd_intf_nets input_data_splitter_M00_AXIS4] [get_bd_intf_nets input_data_splitter/Conn8] [get_bd_intf_nets input_data_splitter_M00_AXIS5] [get_bd_intf_nets input_data_splitter/Conn9] [get_bd_intf_nets input_data_splitter/Conn7] delete_bd_objs [get_bd_intf_pins input_data_splitter/M00_AXIS3] [get_bd_intf_pins input_data_splitter/M00_AXIS4] [get_bd_intf_pins input_data_splitter/M00_AXIS2] [get_bd_intf_pins input_data_splitter/M00_AXIS1] [get_bd_intf_pins input_data_splitter/M00_AXIS] [get_bd_intf_pins input_data_splitter/M00_AXIS5] endgroup connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS] [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS] [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS] [get_bd_intf_pins input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS] set_property location {3.5 1278 -695} [get_bd_cells Cascaded_FlipFlops_0] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/x_new_axis] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/y_new_axis] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/z_new_axis] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vx_new_axis] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vy_new_axis] set_property location {4 1576 -682} [get_bd_cells Cascaded_FlipFlops_0] connect_bd_intf_net [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vz_new_axis] delete_bd_objs [get_bd_intf_nets application_to_accel_1_DT_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_1 endgroup set_property location {2 220 -754} [get_bd_cells Crossbar_Bypass_1x2_1] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_1}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_1}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_1}] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_2/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_2/M01_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_3/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_3/M01_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_4/S00_AXIS] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_1}] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_4/M01_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_5/S00_AXIS] group_bd_cells bypass1x6 [get_bd_cells Crossbar_Bypass_1x2_1] [get_bd_cells Crossbar_Bypass_1x2_2] [get_bd_cells Crossbar_Bypass_1x2_3] [get_bd_cells Crossbar_Bypass_1x2_4] [get_bd_cells Crossbar_Bypass_1x2_5] set_property location {2 365 -414} [get_bd_cells bypass1x6] set_property screensize {138 232} [get_bd_cells bypass1x6] connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 bypass1x6/Crossbar_Bypass_1x2_0 endgroup move_bd_cells [get_bd_cells /] [get_bd_cells bypass1x6/Crossbar_Bypass_1x2_0] undo INFO: [Common 17-17] undo 'move_bd_cells [get_bd_cells /] [get_bd_cells bypass1x6/Crossbar_Bypass_1x2_0]' undo INFO: [Common 17-17] undo 'endgroup' INFO: [Common 17-17] undo 'create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 bypass1x6/Crossbar_Bypass_1x2_0' INFO: [Common 17-17] undo 'startgroup' set_property location {6.5 4283 -215} [get_bd_cells Crossbar_Bypass_1x2_0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_1 endgroup connect_bd_intf_net [get_bd_intf_pins bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_1/M00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/S00_AXIS] [get_bd_intf_pins application_to_accel_1/DT_AXIS] copy_bd_objs / [get_bd_cells {bypass1x6}] set_property location {9 4421 -251} [get_bd_cells bypass1x7] move_bd_cells [get_bd_cells /] [get_bd_cells Fused_Adder_2x1Mux/AXIS_2x1_Mux_1] set_property location {9 4007 -813} [get_bd_cells AXIS_2x1_Mux_1] set_property location {9 3724 -930} [get_bd_cells AXIS_2x1_Mux_1] move_bd_cells [get_bd_cells Fused_Adder_2x1Mux] [get_bd_cells AXIS_2x1_Mux_1] connect_bd_intf_net [get_bd_intf_pins Fused_Adder_2x1Mux/AXIS_2x1_Mux_1/M00_AXIS] -boundary_type upper [get_bd_intf_pins bypass1x7/S00_AXIS] set_property location {9 3741 -757} [get_bd_cells Fused_Adder_2x1Mux] set_property location {5 2375 -1018} [get_bd_cells bypass1x7] set_property location {2 543 -918} [get_bd_cells bypass1x7] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x7/M01_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x7/M00_AXIS] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x7/M00_AXIS1] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x7/M00_AXIS2] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x7/M00_AXIS3] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS] set_property location {2 454 -733} [get_bd_cells bypass1x7] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x7/M00_AXIS4] [get_bd_intf_pins Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS] startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_4 endgroup set_property location {9 3952 -147} [get_bd_cells floating_point_4] set_property -dict [list \ CONFIG.Add_Sub_Value {Add} \ CONFIG.C_Latency {1} \ CONFIG.Maximum_Latency {false} \ ] [get_bd_cells floating_point_4] set_property location {8 3591 -135} [get_bd_cells Fused_2x1Mux_Op_1] connect_bd_net [get_bd_pins floating_point_4/aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_intf_net [get_bd_intf_pins Fused_2x1Mux_Op_1/M00_AXIS] [get_bd_intf_pins floating_point_4/S_AXIS_B] startgroup create_bd_cell -type ip -vlnv ecelrc:user:reg_file_6x1:1.0 reg_file_6x1_0 endgroup connect_bd_net [get_bd_pins reg_file_6x1_0/clk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_6x1_Mux:1.0 AXIS_6x1_Mux_1 endgroup connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M00_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M02_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M03_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S03_AXIS] connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M04_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S04_AXIS] connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M05_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S05_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_1/M00_AXIS] [get_bd_intf_pins floating_point_4/S_AXIS_A] copy_bd_objs / [get_bd_cells {bypass1x7}] connect_bd_intf_net [get_bd_intf_pins floating_point_4/M_AXIS_RESULT] -boundary_type upper [get_bd_intf_pins bypass1x8/S00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x8/M01_AXIS] [get_bd_intf_pins reg_file_6x1_0/S00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x8/M00_AXIS] [get_bd_intf_pins reg_file_6x1_0/S01_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x8/M00_AXIS1] [get_bd_intf_pins reg_file_6x1_0/S02_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x8/M00_AXIS2] [get_bd_intf_pins reg_file_6x1_0/S03_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x8/M00_AXIS3] [get_bd_intf_pins reg_file_6x1_0/S04_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins bypass1x8/M00_AXIS4] [get_bd_intf_pins reg_file_6x1_0/S05_AXIS] report_ip_status -name ip_status report_ip_status -name ip_status upgrade_ip [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_application_to_accel_1_0 (application_to_accel_v1.0 1.0) from revision 3 to revision 1 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet report_ip_status -name ip_status open_project /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_14' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_14' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_14' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_14' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_14' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_1_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_1_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_1_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_1_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_1_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_2_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_2_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_2_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_2_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_2_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_3_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_3_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_3_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_3_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_3_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_4_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_4_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_4_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_4_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_4_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. Please regenerate to continue. INFO: [Common 17-14] Message 'IP_Flow 19-3664' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 9625.359 ; gain = 0.000 ; free physical = 366036 ; free virtual = 379421 update_compile_order -fileset sources_1 close_project create_peripheral ecelrc user controller 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core ecelrc:user:controller:1.0] generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core ecelrc:user:controller:1.0] write_peripheral [ipx::find_open_core ecelrc:user:controller:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0 /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0 /misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_application_to_accel_1_0 (application_to_accel_v1.0 1.0) from revision 1 to revision 3 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet report_ip_status -name ip_status ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ERROR: [BD 5-104] A block design must be open to run this command. Please create/open a block design. ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors. ERROR: [BD 41-1273] Error running can_apply_rule TCL procedure: ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors. ::xilinx.com_bd_rule_sys_mgmt_wiz::can_apply_rule Line 4 ERROR: [BD 5-104] A block design must be open to run this command. Please create/open a block design. ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors. ERROR: [BD 41-1273] Error running can_apply_rule TCL procedure: ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors. ::xilinx.com_bd_rule_sys_mgmt_wiz::can_apply_rule Line 4 current_project ultra96v2_oob current_project application_to_accel_v1_0_project update_compile_order -fileset sources_1 set_property source_mgmt_mode DisplayOnly [current_project] ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. INFO: [IP_Flow 19-3166] Bus Interface 'S00_AXI': References existing memory map 'S00_AXI'. set_property core_revision 4 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3420] Updated ultra96v2_oob_application_to_accel_1_0 to use current project options Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet regenerate_bd_layout startgroup create_bd_cell -type ip -vlnv ecelrc:user:application_to_accel:1.0 application_to_accel_0 endgroup delete_bd_objs [get_bd_cells application_to_accel_0] report_ip_status -name ip_status save_bd_design Wrote : Wrote : ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 5 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 update_ip_catalog -rebuild -scan_changes INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_application_to_accel_1_0 (application_to_accel_v1.0 1.0) from revision 3 to revision 5 WARNING: [IP_Flow 19-4698] Upgrade has added port 'acc_ld_ctr' WARNING: [IP_Flow 19-4698] Upgrade has added port 'acc_select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'add_sel' WARNING: [IP_Flow 19-4698] Upgrade has added port 'div_sel' WARNING: [IP_Flow 19-4698] Upgrade has added port 'dt_select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'forward' WARNING: [IP_Flow 19-4698] Upgrade has added port 'mul_select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'op_select_divide' WARNING: [IP_Flow 19-4698] Upgrade has added port 'op_select_mult' WARNING: [IP_Flow 19-4698] Upgrade has added port 'set_new' WARNING: [IP_Flow 19-4698] Upgrade has added port 'start_calculation' WARNING: [IP_Flow 19-4698] Upgrade has added port 'sum_sel' WARNING: [IP_Flow 19-4698] Upgrade has added port 'v_sel' WARNING: [IP_Flow 19-4698] Upgrade has added port 'vx_in' WARNING: [IP_Flow 19-4698] Upgrade has added port 'vy_in' WARNING: [IP_Flow 19-4698] Upgrade has added port 'vz_in' WARNING: [IP_Flow 19-4698] Upgrade has added port 'x_in' WARNING: [IP_Flow 19-4698] Upgrade has added port 'x_new' WARNING: [IP_Flow 19-4698] Upgrade has added port 'y_in' WARNING: [IP_Flow 19-4698] Upgrade has added port 'y_new' WARNING: [IP_Flow 19-4698] Upgrade has added port 'z_in' WARNING: [IP_Flow 19-4698] Upgrade has added port 'z_new' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'ultra96v2_oob_application_to_accel_1_0'. These changes may impact your design. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'ultra96v2_oob_application_to_accel_1_0' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log', and verify that the upgraded IP is correctly configured. Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet connect_bd_net [get_bd_pins application_to_accel_1/op_select_mult] [get_bd_pins AXIS_6x1_Mux_0/select6x1] delete_bd_objs [get_bd_nets application_to_accel_1_op_select_mult] connect_bd_net [get_bd_pins application_to_accel_1/start_calculation] [get_bd_pins AXIS_6x1_Mux_0/select6x1] set_property location {6 3389 828} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/add_sel] [get_bd_pins Fused_Adder_2x1Mux/AXIS_2x1_Mux_1/select2x1] set_property location {6 4900 666} [get_bd_cells application_to_accel_1] set_property location {6 5249 1156} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/x_in] [get_bd_pins Muxes3x1/AXIS_3x1_Mux_5/select3x1] connect_bd_net [get_bd_pins application_to_accel_1/y_in] [get_bd_pins Muxes3x1/AXIS_3x1_Mux_6/select3x1] connect_bd_net [get_bd_pins application_to_accel_1/z_in] [get_bd_pins Muxes3x1/AXIS_3x1_Mux_4/select3x1] connect_bd_net [get_bd_pins application_to_accel_1/vz_in] [get_bd_pins Muxes3x1/AXIS_3x1_Mux_1/select3x1] connect_bd_net [get_bd_pins application_to_accel_1/vy_in] [get_bd_pins Muxes3x1/AXIS_3x1_Mux_2/select3x1] connect_bd_net [get_bd_pins application_to_accel_1/vx_in] [get_bd_pins Muxes3x1/AXIS_3x1_Mux_3/select3x1] set_property location {7 5354 571} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/start_calculation] [get_bd_pins Cascaded_FlipFlops_0/set_new] connect_bd_net [get_bd_pins application_to_accel_1/forward] [get_bd_pins Cascaded_FlipFlops_0/forward] connect_bd_net [get_bd_pins application_to_accel_1/v_sel] [get_bd_pins AXIS_3x1_Mux_0/select3x1] delete_bd_objs [get_bd_nets application_to_accel_1_start_calculation] connect_bd_net [get_bd_pins application_to_accel_1/op_select_mult] [get_bd_pins Cascaded_FlipFlops_0/set_new] delete_bd_objs [get_bd_nets application_to_accel_1_op_select_mult] connect_bd_net [get_bd_pins application_to_accel_1/op_select_mult] [get_bd_pins Cascaded_FlipFlops_0/set_new] delete_bd_objs [get_bd_nets application_to_accel_1_op_select_mult] connect_bd_net [get_bd_pins Cascaded_FlipFlops_0/set_new] [get_bd_pins application_to_accel_1/set_new] connect_bd_net [get_bd_pins application_to_accel_1/start_calculation] [get_bd_pins force_sm_0/start_calculation] connect_bd_net [get_bd_pins application_to_accel_1/dt_select] [get_bd_pins AXIS_2x1_Mux_0/select2x1] set_property location {10 6844 567} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/op_select_mult] [get_bd_pins Fused_2x1Mux_Op_1/apply_op] connect_bd_net [get_bd_pins application_to_accel_1/op_select_divide] [get_bd_pins Fused_2x1Mux_Op_0/op_select] delete_bd_objs [get_bd_nets application_to_accel_1_op_select_divide] connect_bd_net [get_bd_pins application_to_accel_1/op_select_divide] [get_bd_pins Fused_2x1Mux_Op_0/apply_op] connect_bd_net [get_bd_pins application_to_accel_1/div_sel] [get_bd_pins Fused_2x1Mux_Op_0/op_select] connect_bd_net [get_bd_pins application_to_accel_1/mul_select] [get_bd_pins Fused_2x1Mux_Op_1/op_select] set_property location {14 8293 538} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/acc_ld_ctr] [get_bd_pins reg_file_6x1_0/ld_ctr] connect_bd_net [get_bd_pins application_to_accel_1/acc_select] [get_bd_pins AXIS_6x1_Mux_1/select6x1] set_property location {7 5340 279} [get_bd_cells application_to_accel_1] set_property location {4 3446 76} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/start_calculation] [get_bd_pins AXIS_6x1_Mux_0/select6x1] delete_bd_objs [get_bd_nets application_to_accel_1_start_calculation] connect_bd_net [get_bd_pins AXIS_6x1_Mux_0/select6x1] [get_bd_pins application_to_accel_1/sum_sel] set_property location {7 5378 370} [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins application_to_accel_1/start_calculation] [get_bd_pins force_sm_0/start_calculation] regenerate_bd_layout regenerate_bd_layout save_bd_design Wrote : Wrote : report_ip_status -name ip_status ipx::edit_ip_in_project -upgrade true -name Cascaded_FlipFlops_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/Cascaded_FlipFlops_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Cascaded_FlipFlops_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/Cascaded_FlipFlops_1_0/component.xml' ignored by IP packager. set_property core_revision 7 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:Cascaded_FlipFlops:1.0 [get_ips ultra96v2_oob_Cascaded_FlipFlops_0_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_Cascaded_FlipFlops_0_0 (Cascaded_FlipFlops_v1.0 1.0) from revision 6 to revision 7 WARNING: [IP_Flow 19-4698] Upgrade has added port 'x_deposit' WARNING: [IP_Flow 19-4698] Upgrade has added port 'y_deposit' WARNING: [IP_Flow 19-4698] Upgrade has added port 'z_deposit' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'ultra96v2_oob_Cascaded_FlipFlops_0_0'. These changes may impact your design. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'ultra96v2_oob_Cascaded_FlipFlops_0_0' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log', and verify that the upgraded IP is correctly configured. Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_Cascaded_FlipFlops_0_0] -no_script -sync -force -quiet set_property location {4 1720 703} [get_bd_cells Cascaded_FlipFlops_0] connect_bd_net [get_bd_pins Cascaded_FlipFlops_0/x_deposit] [get_bd_pins application_to_accel_1/x_new] connect_bd_net [get_bd_pins Cascaded_FlipFlops_0/y_deposit] [get_bd_pins application_to_accel_1/y_new] connect_bd_net [get_bd_pins Cascaded_FlipFlops_0/z_deposit] [get_bd_pins application_to_accel_1/z_new] report_ip_status -name ip_status regenerate_bd_layout group_bd_cells custom_mult_accumulate [get_bd_cells floating_point_4] [get_bd_cells reg_file_6x1_0] [get_bd_cells Fused_2x1Mux_Op_1] [get_bd_cells AXIS_6x1_Mux_1] [get_bd_cells bypass1x8] group_bd_cells fused_div_add [get_bd_cells Fused_2x1Mux_Op_0] [get_bd_cells AXIS_6x1_Mux_0] [get_bd_cells bypass1x7] [get_bd_cells Fused_Adder_2x1Mux] regenerate_bd_layout group_bd_cells force_calculator [get_bd_cells floating_point_1] [get_bd_cells force_sm_0] [get_bd_cells floating_point_0] [get_bd_cells floating_point_2] regenerate_bd_layout group_bd_cells RK4_Accelerator [get_bd_cells AXIS_2x1_Mux_0] [get_bd_cells floating_point_3] [get_bd_cells Crossbar_Bypass_1x2_0] [get_bd_cells Crossbar_Bypass_1x2_1] [get_bd_cells Cascaded_FlipFlops_0] [get_bd_cells AXIS_3x1_Mux_0] [get_bd_cells application_to_accel_1] [get_bd_cells bypass1x6] [get_bd_cells input_data_splitter] [get_bd_cells Muxes3x1] [get_bd_cells force_calculator] [get_bd_cells custom_mult_accumulate] [get_bd_cells fused_div_add] regenerate_bd_layout report_ip_status -name ip_status save_bd_design Wrote : Wrote : open_bd_design {/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change WARNING: [IP_Flow 19-474] Invalid Parameter 'Component_Name' INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change startgroup set_property -dict [list \ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {5} \ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \ ] [get_bd_cells zynq_ultra_ps_e_0] INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change endgroup save_bd_design Wrote : Wrote : report_ip_status -name ip_status reset_run ultra96v2_oob_zynq_ultra_ps_e_0_0_synth_1 reset_run synth_1 launch_runs synth_1 -jobs 36 WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.4-0] ultra96v2_oob_zynq_ultra_ps_e_0_0: Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto. This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option. The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow. For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose. INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created. INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM1_FPD'. A default connection has been created. INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_LPD'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/rst_ps8_0_100M . INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/ULTRA96_SYSTEM/Low_Speed_MEZZ/axi_uart16550_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/ULTRA96_SYSTEM/Low_Speed_MEZZ/axi_uart16550_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/force_calculator/force_sm_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/force_calculator/floating_point_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/force_calculator/floating_point_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/force_calculator/floating_point_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/application_to_accel_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/AXIS_6x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Cascaded_FlipFlops_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/AXIS_3x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/AXIS_2x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/floating_point_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/Fused_2x1Mux_Op_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/Fused_Adder_2x1Mux/floating_point_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/Fused_Adder_2x1Mux/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/Fused_Adder_2x1Mux/AXIS_2x1_Mux_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/bypass1x7/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/bypass1x7/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/bypass1x7/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/bypass1x7/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/fused_div_add/bypass1x7/Crossbar_Bypass_1x2_5 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/floating_point_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/reg_file_6x1_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin X_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin Y_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin Z_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin VX_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin VY_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin VZ_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin C_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin DT_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_2x1_Mux_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_2x1_Mux_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_1_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_1_2 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_1_3 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_1_4 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_3x1_Mux_1_5 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_6x1_Mux_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_AXIS_6x1_Mux_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Cascaded_FlipFlops_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_2 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_3 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_4 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_5 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_0_6 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_2 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_3 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_4 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_5 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_6 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_7 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_1_8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_2_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_2_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_3_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_3_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_4_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_4_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_5_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Crossbar_Bypass_1x2_5_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Fused_2x1Mux_Op_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_Fused_2x1Mux_Op_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_application_to_accel_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_axi_uart16550_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_axi_uart16550_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_floating_point_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_floating_point_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_floating_point_0_2 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_floating_point_3_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_floating_point_4_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_floating_point_4_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_force_sm_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_reg_file_6x1_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_rst_ps8_0_100M_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_zynq_ultra_ps_e_0_0 INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork() INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_2x1_Mux_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Cascaded_FlipFlops_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_2_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_axi_uart16550_0_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 52f981d563233844 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_0_0/ultra96v2_oob_axi_uart16550_0_0_stub.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_axi_uart16550_0_0, cache-ID = 52f981d563233844; cache size = 2487.620 MB. INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_2x1_Mux_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_6x1_Mux_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_3_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_zynq_ultra_ps_e_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_4 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_4_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_axi_uart16550_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry 52f981d563233844 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/5/2/52f981d563233844/ultra96v2_oob_axi_uart16550_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_axi_uart16550_1_0/ultra96v2_oob_axi_uart16550_1_0_stub.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_axi_uart16550_1_0, cache-ID = 52f981d563233844; cache size = 2487.620 MB. INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_4_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_floating_point_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_floating_point_3_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_floating_point_4_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_reg_file_6x1_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_1_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_5 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_5_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_1_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_6 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_5_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_force_sm_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_1_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_4 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_7 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Fused_2x1Mux_Op_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_1_4 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_5 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_8 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Fused_2x1Mux_Op_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_3x1_Mux_1_5 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_0_6 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_2_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_AXIS_6x1_Mux_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_1_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Crossbar_Bypass_1x2_3_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_floating_point_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_floating_point_0_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_floating_point_4_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_rst_ps8_0_100M_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry e5fb5e9d048a4c58 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/e/5/e5fb5e9d048a4c58/ultra96v2_oob_rst_ps8_0_100M_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/e/5/e5fb5e9d048a4c58/ultra96v2_oob_rst_ps8_0_100M_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/e/5/e5fb5e9d048a4c58/ultra96v2_oob_rst_ps8_0_100M_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_sim_netlist.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/e/5/e5fb5e9d048a4c58/ultra96v2_oob_rst_ps8_0_100M_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/e/5/e5fb5e9d048a4c58/ultra96v2_oob_rst_ps8_0_100M_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_rst_ps8_0_100M_0/ultra96v2_oob_rst_ps8_0_100M_0_stub.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_rst_ps8_0_100M_0, cache-ID = e5fb5e9d048a4c58; cache size = 2487.620 MB. [Sat May 4 17:22:47 2024] Launched ultra96v2_oob_zynq_ultra_ps_e_0_0_synth_1, ultra96v2_oob_smartconnect_0_0_synth_1, ultra96v2_oob_smartconnect_1_0_synth_1, ultra96v2_oob_force_sm_0_0_synth_1, ultra96v2_oob_floating_point_0_0_synth_1, ultra96v2_oob_floating_point_0_1_synth_1, ultra96v2_oob_floating_point_0_2_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_2_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_1_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_6_synth_1, ultra96v2_oob_Fused_2x1Mux_Op_0_0_synth_1, ultra96v2_oob_Fused_2x1Mux_Op_0_1_synth_1, ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1, ultra96v2_oob_AXIS_3x1_Mux_0_0_synth_1, ultra96v2_oob_AXIS_2x1_Mux_0_1_synth_1, ultra96v2_oob_floating_point_3_0_synth_1, ultra96v2_oob_application_to_accel_1_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_3_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_4_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_0_5_synth_1, ultra96v2_oob_AXIS_6x1_Mux_0_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_3_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_4_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_5_0_synth_1, ultra96v2_oob_floating_point_4_1_synth_1, ultra96v2_oob_reg_file_6x1_0_0_synth_1, ultra96v2_oob_AXIS_6x1_Mux_1_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_8_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_2_1_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_3_1_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_4_1_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_5_1_synth_1, ultra96v2_oob_floating_point_4_0_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_0_synth_1, ultra96v2_oob_AXIS_2x1_Mux_1_0_synth_1, ultra96v2_oob_AXIS_3x1_Mux_1_4_synth_1, ultra96v2_oob_AXIS_3x1_Mux_1_0_synth_1, ultra96v2_oob_AXIS_3x1_Mux_1_1_synth_1, ultra96v2_oob_AXIS_3x1_Mux_1_2_synth_1, ultra96v2_oob_AXIS_3x1_Mux_1_3_synth_1, ultra96v2_oob_AXIS_3x1_Mux_1_5_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_1_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_2_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_3_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_4_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_5_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_6_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_1_7_synth_1, ultra96v2_oob_Crossbar_Bypass_1x2_2_0_synth_1... Run output will be captured here: ultra96v2_oob_zynq_ultra_ps_e_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_zynq_ultra_ps_e_0_0_synth_1/runme.log ultra96v2_oob_smartconnect_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_smartconnect_0_0_synth_1/runme.log ultra96v2_oob_smartconnect_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_smartconnect_1_0_synth_1/runme.log ultra96v2_oob_force_sm_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_force_sm_0_0_synth_1/runme.log ultra96v2_oob_floating_point_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_floating_point_0_0_synth_1/runme.log ultra96v2_oob_floating_point_0_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_floating_point_0_1_synth_1/runme.log ultra96v2_oob_floating_point_0_2_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_floating_point_0_2_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_2_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_2_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_1_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_6_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_6_synth_1/runme.log ultra96v2_oob_Fused_2x1Mux_Op_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Fused_2x1Mux_Op_0_0_synth_1/runme.log ultra96v2_oob_Fused_2x1Mux_Op_0_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Fused_2x1Mux_Op_0_1_synth_1/runme.log ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_0_0_synth_1/runme.log ultra96v2_oob_AXIS_2x1_Mux_0_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_2x1_Mux_0_1_synth_1/runme.log ultra96v2_oob_floating_point_3_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_floating_point_3_0_synth_1/runme.log ultra96v2_oob_application_to_accel_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_application_to_accel_1_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_3_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_3_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_4_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_4_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_0_5_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_0_5_synth_1/runme.log ultra96v2_oob_AXIS_6x1_Mux_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_6x1_Mux_0_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_3_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_3_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_4_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_4_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_5_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_5_0_synth_1/runme.log ultra96v2_oob_floating_point_4_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_floating_point_4_1_synth_1/runme.log ultra96v2_oob_reg_file_6x1_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_reg_file_6x1_0_0_synth_1/runme.log ultra96v2_oob_AXIS_6x1_Mux_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_6x1_Mux_1_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_8_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_8_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_2_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_2_1_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_3_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_3_1_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_4_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_4_1_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_5_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_5_1_synth_1/runme.log ultra96v2_oob_floating_point_4_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_floating_point_4_0_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_0_synth_1/runme.log ultra96v2_oob_AXIS_2x1_Mux_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_2x1_Mux_1_0_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_1_4_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_1_4_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_1_0_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_1_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_1_1_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_1_2_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_1_2_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_1_3_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_1_3_synth_1/runme.log ultra96v2_oob_AXIS_3x1_Mux_1_5_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_AXIS_3x1_Mux_1_5_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_1_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_1_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_2_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_2_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_3_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_3_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_4_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_4_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_5_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_5_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_6_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_6_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_1_7_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_1_7_synth_1/runme.log ultra96v2_oob_Crossbar_Bypass_1x2_2_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Crossbar_Bypass_1x2_2_0_synth_1/runme.log [Sat May 4 17:22:49 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log launch_runs: Time (s): cpu = 00:02:23 ; elapsed = 00:01:57 . Memory (MB): peak = 11031.918 ; gain = 0.000 ; free physical = 355987 ; free virtual = 374247 launch_runs impl_1 -jobs 36 [Sat May 4 17:31:39 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream -jobs 36 [Sat May 4 17:40:10 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log assign_bd_address -target_address_space /zynq_ultra_ps_e_0/Data [get_bd_addr_segs RK4_Accelerator/application_to_accel_1/S00_AXI/S00_AXI_reg] -force Slave segment '/RK4_Accelerator/application_to_accel_1/S00_AXI/S00_AXI_reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0xA000_0000 [ 64K ]>. set_property offset 0x00B0000000 [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_application_to_accel_1_S00_AXI_reg}] save_bd_design Wrote : Wrote : report_ip_status -name ip_status reset_run synth_1 launch_runs synth_1 -jobs 36 WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin X_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin Y_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin Z_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin VX_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin VY_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin VZ_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin C_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin DT_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/application_to_accel_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork() INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 [Sun May 5 10:14:16 2024] Launched ultra96v2_oob_smartconnect_0_0_synth_1, ultra96v2_oob_smartconnect_1_0_synth_1... Run output will be captured here: ultra96v2_oob_smartconnect_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_smartconnect_0_0_synth_1/runme.log ultra96v2_oob_smartconnect_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_smartconnect_1_0_synth_1/runme.log [Sun May 5 10:14:17 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log launch_runs: Time (s): cpu = 00:01:12 ; elapsed = 00:01:14 . Memory (MB): peak = 11516.840 ; gain = 0.000 ; free physical = 356197 ; free virtual = 375032 report_ip_status -name ip_status reset_run synth_1 reset_run ultra96v2_oob_smartconnect_1_0_synth_1 move_bd_cells [get_bd_cells /] [get_bd_cells RK4_Accelerator/floating_point_3] set_property location {3 1812 691} [get_bd_cells floating_point_3] move_bd_cells [get_bd_cells RK4_Accelerator] [get_bd_cells floating_point_3] connect_bd_intf_net [get_bd_intf_pins RK4_Accelerator/floating_point_3/S_AXIS_A] [get_bd_intf_pins RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS] ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. INFO: [IP_Flow 19-3166] Bus Interface 'S00_AXI': References existing memory map 'S00_AXI'. set_property core_revision 6 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3420] Updated ultra96v2_oob_application_to_accel_1_0 to use current project options Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet generate_target all [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/application_to_accel_1 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. generate_target: Time (s): cpu = 00:01:20 ; elapsed = 00:01:18 . Memory (MB): peak = 11656.898 ; gain = 0.000 ; free physical = 356024 ; free virtual = 374879 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry b0f64cd2145c2469 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_0_0, cache-ID = b0f64cd2145c2469; cache size = 2608.140 MB. catch { [ delete_ip_run [get_ips -all ultra96v2_oob_smartconnect_0_0] ] } catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_application_to_accel_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] launch_runs ultra96v2_oob_smartconnect_1_0_synth_1 ultra96v2_oob_application_to_accel_1_0_synth_1 -jobs 36 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 [Sun May 5 10:30:24 2024] Launched ultra96v2_oob_smartconnect_1_0_synth_1, ultra96v2_oob_application_to_accel_1_0_synth_1... Run output will be captured here: ultra96v2_oob_smartconnect_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_smartconnect_1_0_synth_1/runme.log ultra96v2_oob_application_to_accel_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_application_to_accel_1_0_synth_1/runme.log export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet report_ip_status -name ip_status regenerate_bd_layout launch_runs synth_1 -jobs 36 [Sun May 5 10:39:20 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log launch_runs impl_1 -jobs 36 [Sun May 5 10:40:57 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream -jobs 36 [Sun May 5 10:48:46 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log write_hw_platform -fixed -include_bit -force -file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa INFO: [Project 1-1918] Creating Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa ... INFO: [Project 1-1943] The Hardware Platform can be used for Hardware INFO: [Project 1-1941] Successfully created Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa INFO: [Hsi 55-2053] elapsed time for repository (/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/embeddedsw) loading 0 seconds write_hw_platform: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 11766.398 ; gain = 0.000 ; free physical = 355888 ; free virtual = 375081 open_bd_design {/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. INFO: [IP_Flow 19-3166] Bus Interface 'S00_AXI': References existing memory map 'S00_AXI'. set_property core_revision 7 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3420] Updated ultra96v2_oob_application_to_accel_1_0 to use current project options Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet generate_target all [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/application_to_accel_1 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. generate_target: Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 12393.668 ; gain = 0.000 ; free physical = 325881 ; free virtual = 372190 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry b0f64cd2145c2469 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_0_0, cache-ID = b0f64cd2145c2469; cache size = 2707.836 MB. catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fa7ba04312511aa7 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_1_0, cache-ID = fa7ba04312511aa7; cache size = 2707.836 MB. config_ip_cache: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 12393.668 ; gain = 0.000 ; free physical = 325804 ; free virtual = 372181 catch { [ delete_ip_run [get_ips -all ultra96v2_oob_smartconnect_1_0] ] } catch { config_ip_cache -export [get_ips -all ultra96v2_oob_application_to_accel_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] launch_runs ultra96v2_oob_application_to_accel_1_0_synth_1 -jobs 36 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 [Sun May 5 12:03:44 2024] Launched ultra96v2_oob_application_to_accel_1_0_synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_application_to_accel_1_0_synth_1/runme.log export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet report_ip_status -name ip_status reset_run synth_1 launch_runs synth_1 -jobs 36 [Sun May 5 12:05:44 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log launch_runs impl_1 -jobs 36 [Sun May 5 12:07:27 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream -jobs 36 [Sun May 5 12:17:31 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log write_hw_platform -fixed -include_bit -force -file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa INFO: [Project 1-1918] Creating Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa ... INFO: [Project 1-1943] The Hardware Platform can be used for Hardware INFO: [Project 1-1941] Successfully created Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa write_hw_platform: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 12525.742 ; gain = 0.000 ; free physical = 325306 ; free virtual = 371795 ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 current_project ultra96v2_oob current_project application_to_accel_v1_0_project ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. INFO: [IP_Flow 19-3166] Bus Interface 'S00_AXI': References existing memory map 'S00_AXI'. set_property core_revision 8 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3420] Updated ultra96v2_oob_application_to_accel_1_0 to use current project options Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet generate_target all [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/application_to_accel_1 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. generate_target: Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 12898.926 ; gain = 0.000 ; free physical = 325489 ; free virtual = 371959 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry b0f64cd2145c2469 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_0_0, cache-ID = b0f64cd2145c2469; cache size = 2708.926 MB. catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fa7ba04312511aa7 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_1_0, cache-ID = fa7ba04312511aa7; cache size = 2708.926 MB. config_ip_cache: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 12898.926 ; gain = 0.000 ; free physical = 325501 ; free virtual = 371954 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_application_to_accel_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] launch_runs ultra96v2_oob_application_to_accel_1_0_synth_1 -jobs 36 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 [Sun May 5 12:47:15 2024] Launched ultra96v2_oob_application_to_accel_1_0_synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_application_to_accel_1_0_synth_1/runme.log export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet reset_run synth_1 launch_runs synth_1 -jobs 36 [Sun May 5 12:49:12 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log report_ip_status -name ip_status launch_runs impl_1 -jobs 36 [Sun May 5 12:50:48 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream -jobs 36 [Sun May 5 12:59:30 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log write_hw_platform -fixed -include_bit -force -file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa INFO: [Project 1-1918] Creating Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa ... INFO: [Project 1-1943] The Hardware Platform can be used for Hardware INFO: [Project 1-1941] Successfully created Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa write_hw_platform: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 13139.168 ; gain = 0.000 ; free physical = 324677 ; free virtual = 371159 ipx::edit_ip_in_project -upgrade true -name Cascaded_FlipFlops_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/Cascaded_FlipFlops_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Cascaded_FlipFlops_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 8 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 9 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status upgrade_ip [get_ips {ultra96v2_oob_application_to_accel_1_0 ultra96v2_oob_Cascaded_FlipFlops_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_Cascaded_FlipFlops_0_0 (Cascaded_FlipFlops_v1.0 1.0) from revision 7 to revision 8 INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_application_to_accel_1_0 (application_to_accel_v1.0 1.0) from revision 5 to revision 8 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {ultra96v2_oob_application_to_accel_1_0 ultra96v2_oob_Cascaded_FlipFlops_0_0}] -no_script -sync -force -quiet delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_op_select_divide] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_div_sel] connect_bd_net [get_bd_pins RK4_Accelerator/fused_div_add/apply_op] [get_bd_pins RK4_Accelerator/application_to_accel_1/op_select_divide] connect_bd_net [get_bd_pins RK4_Accelerator/application_to_accel_1/div_sel] [get_bd_pins RK4_Accelerator/fused_div_add/op_select] delete_bd_objs [get_bd_nets RK4_Accelerator/apply_op_1] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_div_sel] connect_bd_net [get_bd_pins RK4_Accelerator/fused_div_add/op_select] [get_bd_pins RK4_Accelerator/application_to_accel_1/op_select_divide] connect_bd_net [get_bd_pins RK4_Accelerator/fused_div_add/apply_op] [get_bd_pins RK4_Accelerator/application_to_accel_1/div_sel] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_vx_in] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_vy_in] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_vz_in] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_x_in] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_y_in] delete_bd_objs [get_bd_nets RK4_Accelerator/application_to_accel_1_z_in] move_bd_cells [get_bd_cells /] [get_bd_cells RK4_Accelerator/application_to_accel_1] move_bd_cells [get_bd_cells RK4_Accelerator] [get_bd_cells application_to_accel_1] move_bd_cells [get_bd_cells /] [get_bd_cells RK4_Accelerator/application_to_accel_1] move_bd_cells [get_bd_cells RK4_Accelerator] [get_bd_cells application_to_accel_1] connect_bd_net [get_bd_pins RK4_Accelerator/Muxes3x1/select3x4] [get_bd_pins RK4_Accelerator/application_to_accel_1/x_in] connect_bd_net [get_bd_pins RK4_Accelerator/Muxes3x1/select3x5] [get_bd_pins RK4_Accelerator/application_to_accel_1/y_in] connect_bd_net [get_bd_pins RK4_Accelerator/Muxes3x1/select3x6] [get_bd_pins RK4_Accelerator/application_to_accel_1/z_in] connect_bd_net [get_bd_pins RK4_Accelerator/Muxes3x1/select3x3] [get_bd_pins RK4_Accelerator/application_to_accel_1/vx_in] connect_bd_net [get_bd_pins RK4_Accelerator/Muxes3x1/select3x1] [get_bd_pins RK4_Accelerator/application_to_accel_1/vy_in] connect_bd_net [get_bd_pins RK4_Accelerator/Muxes3x1/select3x2] [get_bd_pins RK4_Accelerator/application_to_accel_1/vz_in] regenerate_bd_layout regenerate_bd_layout regenerate_bd_layout save_bd_design Wrote : Wrote : update_ip_catalog -rebuild -scan_changes INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3422] Upgraded ultra96v2_oob_application_to_accel_1_0 (application_to_accel_v1.0 1.0) from revision 8 to revision 9 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet generate_target all [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/application_to_accel_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/Cascaded_FlipFlops_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. generate_target: Time (s): cpu = 00:01:17 ; elapsed = 00:01:19 . Memory (MB): peak = 14088.633 ; gain = 0.000 ; free physical = 325306 ; free virtual = 371795 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry b0f64cd2145c2469 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_0_0, cache-ID = b0f64cd2145c2469; cache size = 2709.789 MB. catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fa7ba04312511aa7 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_1_0, cache-ID = fa7ba04312511aa7; cache size = 2709.789 MB. config_ip_cache: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 14088.633 ; gain = 0.000 ; free physical = 325273 ; free virtual = 371732 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_application_to_accel_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_Cascaded_FlipFlops_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Cascaded_FlipFlops_0_0 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] launch_runs ultra96v2_oob_application_to_accel_1_0_synth_1 ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1 -jobs 36 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_Cascaded_FlipFlops_0_0 [Sun May 5 13:57:19 2024] Launched ultra96v2_oob_application_to_accel_1_0_synth_1, ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1... Run output will be captured here: ultra96v2_oob_application_to_accel_1_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_application_to_accel_1_0_synth_1/runme.log ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_Cascaded_FlipFlops_0_0_synth_1/runme.log export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet report_ip_status -name ip_status reset_run synth_1 launch_runs synth_1 -jobs 36 [Sun May 5 13:59:23 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log launch_runs impl_1 -jobs 36 [Sun May 5 14:01:56 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream -jobs 36 [Sun May 5 14:10:00 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log write_hw_platform -fixed -include_bit -force -file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa INFO: [Project 1-1918] Creating Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa ... INFO: [Project 1-1943] The Hardware Platform can be used for Hardware INFO: [Project 1-1941] Successfully created Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa write_hw_platform: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 14088.633 ; gain = 0.000 ; free physical = 325288 ; free virtual = 371770 ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. INFO: [IP_Flow 19-3166] Bus Interface 'S00_AXI': References existing memory map 'S00_AXI'. set_property core_revision 10 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:application_to_accel:1.0 [get_ips ultra96v2_oob_application_to_accel_1_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3420] Updated ultra96v2_oob_application_to_accel_1_0 to use current project options Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_1_0] -no_script -sync -force -quiet generate_target all [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. WARNING: [BD 41-2670] Found an incomplete address path from address space '/zynq_ultra_ps_e_0/Data' to master interface '/everything_except_the_accelerator/smartconnect_1/M10_AXI'. Please either complete or remove this path to resolve. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-1356] Slave segment is not assigned into address space . Please use Address Editor to either assign or exclude it. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/X_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Y_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/Z_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VX_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VY_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/VZ_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/C_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/application_to_accel_1/DT_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_6/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/Fused_2x1Mux_Op_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/AXIS_6x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /RK4_Accelerator/custom_mult_accumulate/bypass1x8/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in High-performance Mode. xit::source_ipfile: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 14478.941 ; gain = 0.000 ; free physical = 325281 ; free virtual = 371743 xit::source_ipfile: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 14478.941 ; gain = 0.000 ; free physical = 325272 ; free virtual = 371734 INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_0_0: SmartConnect ultra96v2_oob_smartconnect_0_0 is in High-performance Mode. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/force_calculator/force_sm_0/aresetn (associated clock /RK4_Accelerator/force_calculator/force_sm_0/aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/Cascaded_FlipFlops_0/aresetn (associated clock /RK4_Accelerator/Cascaded_FlipFlops_0/clk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. CRITICAL WARNING: [BD 41-1347] Reset pin /RK4_Accelerator/application_to_accel_1/s00_axi_aresetn (associated clock /RK4_Accelerator/application_to_accel_1/s00_axi_aclk) is connected to asynchronous reset source /zynq_ultra_ps_e_0/pl_resetn0. This may prevent design from meeting timing. Instead it should be connected to reset source /everything_except_the_accelerator/rst_ps8_0_100M/peripheral_aresetn. WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(1) and /everything_except_the_accelerator/smartconnect_0/M01_AXI(16) Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/sim/ultra96v2_oob.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hdl/ultra96v2_oob_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_0_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/bd_0/synth/ultra96v2_oob_smartconnect_0_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_0 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/hw_handoff/ultra96v2_oob_smartconnect_1_0.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/bd_0/synth/ultra96v2_oob_smartconnect_1_0.hwdef INFO: [BD 41-1029] Generation completed for the IP Integrator block everything_except_the_accelerator/smartconnect_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block RK4_Accelerator/application_to_accel_1 . Exporting to file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/hw_handoff/ultra96v2_oob.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/synth/ultra96v2_oob.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/bypass1x6/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS6 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS7 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS8 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS9 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS10 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/input_data_splitter/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /RK4_Accelerator/Muxes3x1/AXIS_3x1_Mux_1 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. generate_target: Time (s): cpu = 00:01:18 ; elapsed = 00:01:21 . Memory (MB): peak = 14478.941 ; gain = 0.000 ; free physical = 325001 ; free virtual = 371438 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_0_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry b0f64cd2145c2469 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/b/0/b0f64cd2145c2469/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_0_0/ultra96v2_oob_smartconnect_0_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_0_0, cache-ID = b0f64cd2145c2469; cache size = 2711.105 MB. catch { config_ip_cache -export [get_ips -all ultra96v2_oob_smartconnect_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6922] IPCACHE: Exporting cached entry fa7ba04312511aa7 to dir: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0 INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0.dcp to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0.dcp INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_stub.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_stub.vhdl INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.v to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.v INFO: [IP_Flow 19-6928] IPCACHE: copied cached file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/ip/2022.2/f/a/fa7ba04312511aa7/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl to /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl. INFO: [IP_Flow 19-6926] IPCACHE: added file to list for BOM: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.gen/sources_1/bd/ultra96v2_oob/ip/ultra96v2_oob_smartconnect_1_0/ultra96v2_oob_smartconnect_1_0_sim_netlist.vhdl INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP ultra96v2_oob_smartconnect_1_0, cache-ID = fa7ba04312511aa7; cache size = 2711.105 MB. config_ip_cache: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 14478.941 ; gain = 0.000 ; free physical = 324598 ; free virtual = 371084 catch { config_ip_cache -export [get_ips -all ultra96v2_oob_application_to_accel_1_0] } INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] launch_runs ultra96v2_oob_application_to_accel_1_0_synth_1 -jobs 36 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: ultra96v2_oob_application_to_accel_1_0 [Sun May 5 14:49:39 2024] Launched ultra96v2_oob_application_to_accel_1_0_synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/ultra96v2_oob_application_to_accel_1_0_synth_1/runme.log export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd] -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet report_ip_status -name ip_status reset_run synth_1 launch_runs synth_1 -jobs 36 [Sun May 5 14:51:20 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/synth_1/runme.log launch_runs impl_1 -jobs 36 [Sun May 5 14:52:47 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream -jobs 36 [Sun May 5 15:01:14 2024] Launched impl_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/runme.log write_hw_platform -fixed -include_bit -force -file /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa INFO: [Project 1-1918] Creating Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa ... INFO: [Project 1-1943] The Hardware Platform can be used for Hardware INFO: [Project 1-1941] Successfully created Hardware Platform: /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.runs/impl_1/ultra96v2_oob_wrapper.xsa write_hw_platform: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 14478.941 ; gain = 0.000 ; free physical = 325181 ; free virtual = 371672 ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/controller_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 close_project report_ip_status -name ip_status