#----------------------------------------------------------- # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 # Start of session at: Fri May 3 05:51:13 2024 # Process ID: 2146757 # Current directory: /misc/scratch/ahermez/Final_Project # Command line: vivado # Log file: /misc/scratch/ahermez/Final_Project/vivado.log # Journal file: /misc/scratch/ahermez/Final_Project/vivado.jou # Running On: kamek.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404276 MB #----------------------------------------------------------- start_gui WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0_sim_netlist.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1_sim_netlist.vhdl'. Please regenerate to continue. INFO: [Common 17-14] Message 'IP_Flow 19-3664' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 7493.328 ; gain = 368.949 ; free physical = 366745 ; free virtual = 380106 update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} Reading block design file ... Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_0 Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_1 Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_2 Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_3 Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_4 Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_5 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_5 Adding component instance block -- ecelrc:user:AXIS_6x1_Mux:1.0 - AXIS_6x1_Mux_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:Fused_2x1Mux_Op:1.0 - Fused_2x1Mux_Op_0 Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0 Adding component instance block -- ecelrc:user:AXIS_2x1_Mux:1.0 - AXIS_2x1_Mux_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4 Adding component instance block -- ecelrc:user:AXIS_2x1_Mux:1.0 - AXIS_2x1_Mux_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_2 Adding component instance block -- ecelrc:user:force_sm:1.0 - force_sm_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_3 Adding component instance block -- ecelrc:user:reg_file_6x1:1.0 - reg_file_6x1_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0 Adding component instance block -- ecelrc:user:Fused_2x1Mux_Op:1.0 - Fused_2x1Mux_Op_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_1 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1 Adding component instance block -- ecelrc:user:AXIS_6x1_Mux:1.0 - AXIS_6x1_Mux_1 Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:Cascaded_FlipFlops:1.0 - Cascaded_FlipFlops_0 Successfully read diagram from block design file set_property library xil_defaultlib [get_files] generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] INFO: [BD 41-1662] The design 'design_4.bd' is already validated. Therefore parameter propagation will not be re-run. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_2x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/floating_point_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/floating_point_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/floating_point_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block reg_file_6x1_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter1/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter1/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter1/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter1/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter1/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block floating_point_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Fused_2x1Mux_Op_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block dt_multiplier/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block acc_mux/AXIS_6x1_Mux_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block acc_mux/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Cascaded_FlipFlops_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' INFO: [Vivado 12-12490] The selected simulation model for 'design_4_AXIS_2x1_Mux_0_1' IP changed to 'rtl' from '', the simulation run directory will be deleted. WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dbfe/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dbfe/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:21 ; elapsed = 00:00:10 . Memory (MB): peak = 9738.449 ; gain = 0.000 ; free physical = 366440 ; free virtual = 379821 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 9738.449 ; gain = 0.000 ; free physical = 366342 ; free virtual = 379721 current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} current_wave_config {Untitled 1} Untitled 1 add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dbfe/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dbfe/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:20 ; elapsed = 00:00:10 . Memory (MB): peak = 9738.449 ; gain = 0.000 ; free physical = 366271 ; free virtual = 379657 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 9738.449 ; gain = 0.000 ; free physical = 366226 ; free virtual = 379607 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 9 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Reading block design file ... Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_1 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_2 Adding component instance block -- ecelrc:user:force_sm:1.0 - force_sm_0 Successfully read diagram from block design file Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 8 to revision 9 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 8 to revision 9 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/aaa7/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/aaa7/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:21 ; elapsed = 00:00:11 . Memory (MB): peak = 10576.691 ; gain = 0.000 ; free physical = 366176 ; free virtual = 379562 INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:31 ; elapsed = 00:00:18 . Memory (MB): peak = 10576.691 ; gain = 0.000 ; free physical = 366144 ; free virtual = 379526 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 300 ns open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 current_project FP_Unit_Test open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} Reading block design file ... Adding component instance block -- xilinx.com:ip:floating_point:7.1 - blocking_fpadder Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0 Adding component instance block -- ecelrc:user:AXIS_2x1_Mux:1.0 - AXIS_2x1_Mux_0 Adding component instance block -- ecelrc:user:AXIS_6x1_Mux:1.0 - AXIS_6x1_Mux_0 Successfully read diagram from block design file current_bd_design [get_bd_designs design_1] current_bd_design [get_bd_designs design_3] close_bd_design [get_bd_designs design_3] Wrote : current_bd_design [get_bd_designs design_4] current_bd_design [get_bd_designs design_1] current_fileset -simset [ get_filesets sim_2 ] reset_simulation -simset sim_2 -mode behavioral INFO: [Vivado 12-2266] Removing simulation data... INFO: [Vivado 12-2267] Reset complete generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd] Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/sim/design_1.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.hwdef WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/sim/design_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/design_1.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/sim/design_1.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_force_sm_0_0/design_1_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_floating_point_0_1/design_1_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_floating_point_1_0/design_1_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_floating_point_2_0/design_1_floating_point_2_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/design_1_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_0_1/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_0_1/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_0_1/sim/design_1_floating_point_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_1_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_1_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_1_0/sim/design_1_floating_point_1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_2_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_2_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_2_0/sim/design_1_floating_point_2_0.v'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_2 ] Command: launch_simulation -simset sim_2 INFO: [Vivado 12-12493] Simulation top is 'tb_force_state_machine' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_2' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_force_state_machine' in fileset 'sim_2'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_2'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' xvlog --incr --relax -prj tb_force_state_machine_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_0_1/sim/design_1_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_1_0/sim/design_1_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_2_0/sim/design_1_floating_point_2_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_2_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ipshared/aaa7/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ipshared/aaa7/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_force_sm_0_0/sim/design_1_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_2/new/tb_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_force_state_machine_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_force_state_machine_behav xil_defaultlib.tb_force_state_machine xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_force_state_machine_behav xil_defaultlib.tb_force_state_machine xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_1_floating_point_0_1 Compiling module xil_defaultlib.design_1_floating_point_1_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_1_floating_point_2_0 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_1_force_sm_0_0 Compiling module xil_defaultlib.design_1 Compiling module xil_defaultlib.design_1_wrapper Compiling module xil_defaultlib.tb_force_state_machine Compiling module xil_defaultlib.glbl Built simulation snapshot tb_force_state_machine_behav execute_script: Time (s): cpu = 00:00:20 ; elapsed = 00:00:10 . Memory (MB): peak = 10576.691 ; gain = 0.000 ; free physical = 366116 ; free virtual = 379503 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_force_state_machine_behav -key {Behavioral:sim_2:Functional:tb_force_state_machine} -tclbatch {tb_force_state_machine.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_4.protoinst for the following reason(s): There are no instances of module "design_4" in the design. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_1/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_1/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_1/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/y_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/z_axis Time resolution is 1 ps source tb_force_state_machine.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_force_state_machine_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 10576.691 ; gain = 0.000 ; free physical = 366107 ; free virtual = 379490 current_wave_config {Untitled 4} Untitled 4 add_wave {{/tb_force_state_machine/uut/design_1_i/force_sm_0/inst/state_machine/save_res}} current_wave_config {Untitled 4} Untitled 4 add_wave {{/tb_force_state_machine/uut/design_1_i/force_sm_0/inst/state_machine/current_state}} current_wave_config {Untitled 4} Untitled 4 add_wave {{/tb_force_state_machine/uut/design_1_i/force_sm_0/inst/state_machine/next_state}} current_wave_config {Untitled 4} Untitled 4 add_wave {{/tb_force_state_machine/uut/design_1_i/force_sm_0/inst/state_machine/result}} restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns current_project force_sm_v1_0_project ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 10 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' close_sim INFO: [Simtcl 6-16] Simulation closed report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 9 to revision 10 Wrote : Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 9 to revision 10 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd] Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/sim/design_1.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.hwdef WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/sim/design_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/design_1.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/synth/design_1.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/sim/design_1.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_force_sm_0_0/design_1_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_floating_point_0_1/design_1_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_floating_point_1_0/design_1_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/ip/design_1_floating_point_2_0/design_1_floating_point_2_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/design_1_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_0_1/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_0_1/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_0_1/sim/design_1_floating_point_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_1_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_1_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_1_0/sim/design_1_floating_point_1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_2_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_2_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/ip/design_1_floating_point_2_0/sim/design_1_floating_point_2_0.v'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_2 ] Command: launch_simulation -simset sim_2 INFO: [Vivado 12-12493] Simulation top is 'tb_force_state_machine' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_2' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_force_state_machine' in fileset 'sim_2'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_2'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' xvlog --incr --relax -prj tb_force_state_machine_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_0_1/sim/design_1_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_1_0/sim/design_1_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_2_0/sim/design_1_floating_point_2_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_2_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ipshared/e51f/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ipshared/e51f/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_force_sm_0_0/sim/design_1_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_2/new/tb_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_force_state_machine xvhdl --incr --relax -prj tb_force_state_machine_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_force_state_machine_behav xil_defaultlib.tb_force_state_machine xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_force_state_machine_behav xil_defaultlib.tb_force_state_machine xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_1_floating_point_0_1 Compiling module xil_defaultlib.design_1_floating_point_1_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_1_floating_point_2_0 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_1_force_sm_0_0 Compiling module xil_defaultlib.design_1 Compiling module xil_defaultlib.design_1_wrapper Compiling module xil_defaultlib.tb_force_state_machine Compiling module xil_defaultlib.glbl Built simulation snapshot tb_force_state_machine_behav execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:10 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365971 ; free virtual = 379358 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_force_state_machine_behav -key {Behavioral:sim_2:Functional:tb_force_state_machine} -tclbatch {tb_force_state_machine.tcl} -protoinst "protoinst_files/design_3.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_1/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_1/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_1/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//floating_point_2/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/y_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_force_state_machine/uut/design_1_i//force_sm_0/z_axis Time resolution is 1 ps source tb_force_state_machine.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_force_state_machine_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365951 ; free virtual = 379334 report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed reset_simulation -simset sim_2 -mode behavioral INFO: [Vivado 12-2266] Removing simulation data... INFO: [Vivado 12-2267] Reset complete launch_simulation -simset [get_filesets sim_2 ] Command: launch_simulation -simset sim_2 INFO: [Vivado 12-12493] Simulation top is 'tb_force_state_machine' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_2' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_force_state_machine' in fileset 'sim_2'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_2'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim' xvlog --incr --relax -prj tb_force_state_machine_vlog.prj INFO: [Common 17-41] Interrupt caught. Command should exit soon. INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_0_1/sim/design_1_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_1_0/sim/design_1_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_floating_point_2_0/sim/design_1_floating_point_2_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_floating_point_2_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ipshared/e51f/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ipshared/e51f/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/ip/design_1_force_sm_0_0/sim/design_1_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_1_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_2/new/tb_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_2/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_force_state_machine_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [Common 17-344] 'execute_script' was cancelled INFO: [Vivado 12-5357] 'compile' step aborted INFO: [Common 17-344] 'launch_simulation' was cancelled current_fileset -simset [ get_filesets sim_6 ] close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e51f/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e51f/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:23 ; elapsed = 00:00:10 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365884 ; free virtual = 379264 INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -protoinst "protoinst_files/design_1.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_1.protoinst for the following reason(s): There are no instances of module "design_1" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:32 ; elapsed = 00:00:17 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365866 ; free virtual = 379242 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 300 ns open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} relaunch_sim Command: launch_simulation -step compile -simset sim_6 -mode behavioral INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e51f/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e51f/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '4' seconds Command: launch_simulation -step elaborate -simset sim_6 -mode behavioral INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365800 ; free virtual = 379180 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds launch_simulation: Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365800 ; free virtual = 379180 INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_1.protoinst for the following reason(s): There are no instances of module "design_1" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 10701.738 ; gain = 0.000 ; free physical = 365788 ; free virtual = 379165 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} report_ip_status -name ip_status report_ip_status -name ip_status ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 11 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 10 to revision 11 Wrote : Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 10 to revision 11 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/33d9/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/33d9/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:21 ; elapsed = 00:00:10 . Memory (MB): peak = 10870.820 ; gain = 0.000 ; free physical = 365771 ; free virtual = 379152 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:17 . Memory (MB): peak = 10870.820 ; gain = 0.000 ; free physical = 365756 ; free virtual = 379133 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 300 ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 12 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 11 to revision 12 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 11 to revision 12 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dec6/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dec6/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 11078.922 ; gain = 0.000 ; free physical = 365752 ; free virtual = 379134 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 11078.922 ; gain = 0.000 ; free physical = 365743 ; free virtual = 379120 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 300 ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dec6/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/dec6/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:21 ; elapsed = 00:00:10 . Memory (MB): peak = 11078.922 ; gain = 0.000 ; free physical = 365748 ; free virtual = 379130 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:18 . Memory (MB): peak = 11078.922 ; gain = 0.000 ; free physical = 365737 ; free virtual = 379115 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 13 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 12 to revision 13 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 12 to revision 13 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/22b2/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/22b2/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 11273.020 ; gain = 0.000 ; free physical = 365739 ; free virtual = 379122 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:31 ; elapsed = 00:00:17 . Memory (MB): peak = 11273.020 ; gain = 0.000 ; free physical = 365727 ; free virtual = 379106 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 14 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 13 to revision 14 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 13 to revision 14 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/b223/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/b223/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:21 ; elapsed = 00:00:10 . Memory (MB): peak = 11347.059 ; gain = 0.000 ; free physical = 365720 ; free virtual = 379104 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 11347.059 ; gain = 0.000 ; free physical = 365705 ; free virtual = 379084 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 300 ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 15 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 14 to revision 15 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 14 to revision 15 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/6646/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/6646/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '4' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:23 ; elapsed = 00:00:10 . Memory (MB): peak = 11497.129 ; gain = 0.000 ; free physical = 365702 ; free virtual = 379087 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 145 ns Iteration: 10000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 11497.129 ; gain = 0.000 ; free physical = 365695 ; free virtual = 379075 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml' ignored by IP packager. set_property core_revision 16 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 15 to revision 16 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_force_sm_0_0 (force_sm_v1.0 1.0) from revision 15 to revision 16 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_4_force_sm_0_0}] -no_script -sync -force -quiet report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block F_function/force_sm_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/design_4_AXIS_2x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_3/design_4_floating_point_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_force_sm_0_0/design_4_force_sm_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_2/design_4_floating_point_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_4/design_4_floating_point_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_reg_file_6x1_0_0/design_4_reg_file_6x1_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/design_4_Crossbar_Bypass_1x2_0_15.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/design_4_Crossbar_Bypass_1x2_1_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/design_4_Crossbar_Bypass_1x2_2_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/design_4_Crossbar_Bypass_1x2_3_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/design_4_Crossbar_Bypass_1x2_4_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_5/design_4_floating_point_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/design_4_Fused_2x1Mux_Op_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/design_4_Crossbar_Bypass_1x2_1_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/design_4_AXIS_6x1_Mux_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/design_4_Crossbar_Bypass_1x2_0_16.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/bff9/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/bff9/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '4' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:22 ; elapsed = 00:00:11 . Memory (MB): peak = 11852.301 ; gain = 0.000 ; free physical = 365684 ; free virtual = 379069 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:30 ; elapsed = 00:00:18 . Memory (MB): peak = 11852.301 ; gain = 0.000 ; free physical = 365678 ; free virtual = 379058 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_6 ] Command: launch_simulation -simset sim_6 INFO: [Vivado 12-12493] Simulation top is 'tb_main_system' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_6' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_main_system' in fileset 'sim_6'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_6'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xvlog --incr --relax -prj tb_main_system_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_1/sim/design_4_AXIS_2x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_3/sim/design_4_floating_point_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/bff9/hdl/F_force_state_machine.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module F_force_state_machine INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/bff9/hdl/force_sm_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module force_sm_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_force_sm_0_0/sim/design_4_force_sm_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_force_sm_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_2/sim/design_4_floating_point_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_4/sim/design_4_floating_point_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_file_6x1_v1_0 WARNING: [VRFC 10-3380] identifier 'reg_0' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:121] WARNING: [VRFC 10-3380] identifier 'reg_1' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:122] WARNING: [VRFC 10-3380] identifier 'reg_2' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:123] WARNING: [VRFC 10-3380] identifier 'reg_3' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:124] WARNING: [VRFC 10-3380] identifier 'reg_4' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:125] WARNING: [VRFC 10-3380] identifier 'reg_5' is used before its declaration [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/4c2d/hdl/reg_file_6x1_v1_0.v:126] INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_reg_file_6x1_0_0/sim/design_4_reg_file_6x1_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_reg_file_6x1_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_15/sim/design_4_Crossbar_Bypass_1x2_0_15.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_15 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_2/sim/design_4_Crossbar_Bypass_1x2_1_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_2/sim/design_4_Crossbar_Bypass_1x2_2_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_2/sim/design_4_Crossbar_Bypass_1x2_3_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_2/sim/design_4_Crossbar_Bypass_1x2_4_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_5/sim/design_4_floating_point_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_1/sim/design_4_Fused_2x1Mux_Op_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_3/sim/design_4_Crossbar_Bypass_1x2_1_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_1_0/sim/design_4_AXIS_6x1_Mux_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_16/sim/design_4_Crossbar_Bypass_1x2_0_16.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_16 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/ca35/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module F_function_imp_1WTTNQA INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module acc_mux_imp_D21T52 INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter1_imp_1E6507C INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module dt_multiplier_imp_17FTHIG INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_main_system xvhdl --incr --relax -prj tb_main_system_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_main_system_behav xil_defaultlib.tb_main_system xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package unisim.vcomponents Compiling package mult_gen_v12_0_18.dsp_pkg Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_1 Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_2 Compiling module xil_defaultlib.design_4_floating_point_0_3 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_3to1 [\axi_slave_3to1(c_a_tdata_width=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_4 Compiling module xil_defaultlib.F_force_state_machine Compiling module xil_defaultlib.force_sm_v1_0 Compiling module xil_defaultlib.design_4_force_sm_0_0 Compiling module xil_defaultlib.F_function_imp_1WTTNQA Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_1 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.acc_mux_imp_D21T52 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_2 Compiling module xil_defaultlib.constant_splitter1_imp_1E6507C Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_3 Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.dt_multiplier_imp_17FTHIG Compiling module xil_defaultlib.design_4_floating_point_0_5 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.reg_file_6x1_v1_0 Compiling module xil_defaultlib.design_4_reg_file_6x1_0_0 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_main_system Compiling module xil_defaultlib.glbl Built simulation snapshot tb_main_system_behav execute_script: Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 11852.301 ; gain = 0.000 ; free physical = 365683 ; free virtual = 379069 INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_6/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_main_system_behav -key {Behavioral:sim_6:Functional:tb_main_system} -tclbatch {tb_main_system.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_2/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/floating_point_3/S_AXIS_OPERATION INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/A_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/B_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/C_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/D_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/E_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/F_INPUT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/OPERATION_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/RESULT_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/a_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/b_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/c_result_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/const_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/x_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_main_system/uut/design_4_i//F_function/force_sm_0/y_axis INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_main_system/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_main_system.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_main_system_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:32 ; elapsed = 00:00:18 . Memory (MB): peak = 11852.301 ; gain = 0.000 ; free physical = 365678 ; free virtual = 379060 add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz_new add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/x add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/y add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/z add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vx add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vy add_wave {{/tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz}} /tb_main_system/uut/design_4_i/Cascaded_FlipFlops_0/inst/vz add_wave {{/tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata}} /tb_main_system/uut/design_4_i/dt_multiplier/floating_point_1/m_axis_result_tdata add_wave {{/tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata}} /tb_main_system/uut/design_4_i/F_function/force_sm_0/result_axis_tdata restart INFO: [Wavedata 42-604] Simulation restarted run 600 ns open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} open_project /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 11852.301 ; gain = 0.000 ; free physical = 365565 ; free virtual = 378947 update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd} Reading block design file ... Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0 Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1 Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3 Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0 Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1 Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_0 Adding component instance block -- avnet.com:ip:PWM_w_Int:1.0 - PWM_w_Int_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9 Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_0 Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - axi_bram_ctrl_1 Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1 Adding component instance block -- user.org:user:AXI4_BURST_MASTER:1.0 - AXI4_BURST_MASTER_0 Successfully read diagram from block design file ipx::edit_ip_in_project -upgrade true -name AXI4_BURST_MASTER_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/AXI4_BURST_MASTER_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXI4_BURST_MASTER_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 24 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' create_peripheral ecelrc user user_to_accelerator 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core ecelrc:user:user_to_accelerator:1.0] set_property VALUE 32 [ipx::get_bus_parameters WIZ_NUM_REG -of_objects [ipx::get_bus_interfaces S00_AXI -of_objects [ipx::find_open_core ecelrc:user:user_to_accelerator:1.0]]] generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core ecelrc:user:user_to_accelerator:1.0] write_peripheral [ipx::find_open_core ecelrc:user:user_to_accelerator:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. delete_bd_objs [get_bd_intf_nets smartconnect_1_M09_AXI] [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_cells BRAM] delete_bd_objs [get_bd_intf_nets smartconnect_1_M10_AXI] [get_bd_intf_nets AXI4_BURST_MASTER_0_M00_AXI] [get_bd_cells AXI4_BURST_MASTER_0] set_property location {2 915 834} [get_bd_cells rst_ps8_0_100M] startgroup create_bd_cell -type ip -vlnv ecelrc:user:user_to_accelerator:1.0 user_to_accelerator_0 endgroup connect_bd_intf_net [get_bd_intf_pins user_to_accelerator_0/S00_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI] apply_bd_automation -rule xilinx.com:bd_rule:sys_mgmt_wiz -config {USE_Vp_Vn "Vp_Vn" } [get_bd_cells ULTRA96_SYSTEM/SYS_MGMT/system_management_wiz_0] ERROR: [Common 17-167] Type error ERROR: [BD 41-1273] Error running apply_rule TCL procedure: ERROR: [Common 17-167] Type error get_board_intf Line 12 INFO: [BD 5-145] Automation rule xilinx.com:bd_rule:sys_mgmt_wiz was not applied to object system_management_wiz_0 INFO: [Common 17-17] undo 'apply_bd_automation -rule xilinx.com:bd_rule:sys_mgmt_wiz -config {USE_Vp_Vn "Vp_Vn" } [get_bd_cells ULTRA96_SYSTEM/SYS_MGMT/system_management_wiz_0]' ERROR: [Common 17-39] 'apply_bd_automation' failed due to earlier errors. apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/zynq_ultra_ps_e_0/pl_clk0 (250 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins user_to_accelerator_0/s00_axi_aclk] connect_bd_intf_net [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins smartconnect_1/M09_AXI] current_project FP_Unit_Test report_ip_status -name ip_status group_bd_cells accelerator [get_bd_cells AXIS_2x1_Mux_0] [get_bd_cells reg_file_6x1_0] [get_bd_cells AXIS_6x1_Mux_0] [get_bd_cells Cascaded_FlipFlops_0] [get_bd_cells AXIS_3x1_Mux_0] [get_bd_cells Fused_2x1Mux_Op_0] [get_bd_cells floating_point_0] [get_bd_cells Mux2x1_div] [get_bd_cells constant_splitter] [get_bd_cells Mux2x1_adder_out6] [get_bd_cells F_function] [get_bd_cells dt_multiplier] [get_bd_cells AXIS_3x1_Muxes] [get_bd_cells constant_splitter1] [get_bd_cells acc_mux] [get_bd_cells input_split] current_project ultra96v2_oob group_bd_cells everything_except_the_accelerator [get_bd_cells smartconnect_0] [get_bd_cells smartconnect_1] [get_bd_cells rst_ps8_0_100M] [get_bd_cells xlconcat_0] [get_bd_cells ULTRA96_SYSTEM] INFO: [BD 41-2804] Updated PFM.CLOCK attribute on /zynq_ultra_ps_e_0, replaced old name /rst_ps8_0_100M with new name /everything_except_the_accelerator/rst_ps8_0_100M startgroup create_bd_cell -type ip -vlnv ecelrc:user:force_sm:1.0 force_sm_0 endgroup startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 endgroup set_property -dict [list \ CONFIG.C_Latency {1} \ CONFIG.C_Mult_Usage {Full_Usage} \ CONFIG.C_Rate {1} \ CONFIG.C_Result_Exponent_Width {8} \ CONFIG.C_Result_Fraction_Width {24} \ CONFIG.Maximum_Latency {false} \ CONFIG.Operation_Type {Multiply} \ CONFIG.Result_Precision_Type {Single} \ ] [get_bd_cells floating_point_0] copy_bd_objs / [get_bd_cells {floating_point_0}] copy_bd_objs / [get_bd_cells {floating_point_0}] set_property location {2 711 31} [get_bd_cells floating_point_2] set_property -dict [list \ CONFIG.C_Latency {1} \ CONFIG.C_Mult_Usage {Full_Usage} \ CONFIG.C_Rate {1} \ CONFIG.C_Result_Exponent_Width {8} \ CONFIG.C_Result_Fraction_Width {24} \ CONFIG.Operation_Type {Add_Subtract} \ CONFIG.Result_Precision_Type {Single} \ ] [get_bd_cells floating_point_2] connect_bd_intf_net [get_bd_intf_pins force_sm_0/A_INPUT_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_A] connect_bd_intf_net [get_bd_intf_pins force_sm_0/B_INPUT_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins force_sm_0/C_INPUT_AXIS] [get_bd_intf_pins floating_point_1/S_AXIS_A] connect_bd_intf_net [get_bd_intf_pins force_sm_0/D_INPUT_AXIS] [get_bd_intf_pins floating_point_1/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins force_sm_0/E_INPUT_AXIS] [get_bd_intf_pins floating_point_2/S_AXIS_A] connect_bd_intf_net [get_bd_intf_pins force_sm_0/F_INPUT_AXIS] [get_bd_intf_pins floating_point_2/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins force_sm_0/OPERATION_AXIS] [get_bd_intf_pins floating_point_2/S_AXIS_OPERATION] connect_bd_intf_net [get_bd_intf_pins floating_point_2/M_AXIS_RESULT] [get_bd_intf_pins force_sm_0/c_result_axis] connect_bd_intf_net [get_bd_intf_pins floating_point_1/M_AXIS_RESULT] [get_bd_intf_pins force_sm_0/b_result_axis] connect_bd_intf_net [get_bd_intf_pins floating_point_0/M_AXIS_RESULT] [get_bd_intf_pins force_sm_0/a_result_axis] connect_bd_net [get_bd_pins floating_point_2/aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins floating_point_1/aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins floating_point_0/aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] ipx::edit_ip_in_project -upgrade true -name user_to_accelerator_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/user_to_accelerator_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::add_bus_interface X_AXIS [ipx::current_core] set_property abstraction_type_vlnv xilinx.com:interface:axis_rtl:1.0 [ipx::get_bus_interfaces X_AXIS -of_objects [ipx::current_core]] set_property bus_type_vlnv xilinx.com:interface:axis:1.0 [ipx::get_bus_interfaces X_AXIS -of_objects [ipx::current_core]] set_property interface_mode master [ipx::get_bus_interfaces X_AXIS -of_objects [ipx::current_core]] set_property display_name X_AXIS [ipx::get_bus_interfaces X_AXIS -of_objects [ipx::current_core]] ipx::remove_bus_interface X_AXIS [ipx::current_core] ipx::unload_core /misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0/component.xml close_project delete_bd_objs [get_bd_intf_nets smartconnect_0_M00_AXI] [get_bd_nets rst_ps8_0_100M_peripheral_aresetn] [get_bd_cells user_to_accelerator_0] create_peripheral ecelrc user appl_to_accel 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface X_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface Y_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface Z_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface VX_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface VY_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface VZ_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface C_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] add_peripheral_interface DT_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] write_peripheral [ipx::find_open_core ecelrc:user:appl_to_accel:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0 /misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. startgroup create_bd_cell -type ip -vlnv ecelrc:user:appl_to_accel:1.0 appl_to_accel_0 endgroup ipx::edit_ip_in_project -upgrade true -name appl_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/appl_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_C_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_DT_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_VX_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_VY_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_VZ_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_X_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_Y_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_Z_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_C_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_DT_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_VX_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_VY_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_VZ_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_X_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_Y_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_Z_AXIS.v} add_files -norecurse /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v update_compile_order -fileset sources_1 set_property top appl_to_accel_v1_0 [current_fileset] update_compile_order -fileset sources_1 WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_S00_AXI.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_S00_AXI.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_S00_AXI.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_S00_AXI.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_S00_AXI.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0_S00_AXI.v:] WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0/hdl/appl_to_accel_v1_0.v:] update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 close_project delete_bd_objs [get_bd_cells appl_to_accel_0] create_peripheral ecelrc user application_to_accel 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXI -interface_mode slave -axi_type lite [ipx::find_open_core ecelrc:user:application_to_accel:1.0] set_property VALUE 32 [ipx::get_bus_parameters WIZ_NUM_REG -of_objects [ipx::get_bus_interfaces S00_AXI -of_objects [ipx::find_open_core ecelrc:user:application_to_accel:1.0]]] add_peripheral_interface X_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface Y_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface Z_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface VX_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface VY_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface VZ_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface C_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] add_peripheral_interface DT_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:application_to_accel:1.0] generate_peripheral -driver -bfm_example_design -debug_hw_example_design [ipx::find_open_core ecelrc:user:application_to_accel:1.0] write_peripheral [ipx::find_open_core ecelrc:user:application_to_accel:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 /misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0 /misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. startgroup create_bd_cell -type ip -vlnv ecelrc:user:application_to_accel:1.0 application_to_accel_0 endgroup ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 set_property top application_to_accel_v1_0 [current_fileset] update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VX_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_C_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_DT_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VY_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VZ_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_X_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Y_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Z_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VX_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_C_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_DT_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VY_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VZ_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_X_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Y_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Z_AXIS.v} ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_X_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Y_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Z_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VX_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VY_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VZ_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_C_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_DT_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_X_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Y_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_Z_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VX_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VY_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_VZ_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_C_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/hdl/application_to_accel_v1_0_DT_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml' ignored by IP packager. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (x_axis_tlast x_axis_tstrb) were removed from the interface 'X_AXIS'. Please review the IP interface 'X_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (y_axis_tlast y_axis_tstrb) were removed from the interface 'Y_AXIS'. Please review the IP interface 'Y_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (z_axis_tlast z_axis_tstrb) were removed from the interface 'Z_AXIS'. Please review the IP interface 'Z_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (vx_axis_tlast vx_axis_tstrb) were removed from the interface 'VX_AXIS'. Please review the IP interface 'VX_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (vy_axis_tlast vy_axis_tstrb) were removed from the interface 'VY_AXIS'. Please review the IP interface 'VY_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (vz_axis_tlast vz_axis_tstrb) were removed from the interface 'VZ_AXIS'. Please review the IP interface 'VZ_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (c_axis_tlast c_axis_tstrb) were removed from the interface 'C_AXIS'. Please review the IP interface 'C_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (dt_axis_tlast dt_axis_tstrb) were removed from the interface 'DT_AXIS'. Please review the IP interface 'DT_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (dt_axis_aresetn) was removed from the interface 'DT_AXIS_RST'. Please review the IP interface 'DT_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (dt_axis_aclk) was removed from the interface 'DT_AXIS_CLK'. Please review the IP interface 'DT_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (vz_axis_aresetn) was removed from the interface 'VZ_AXIS_RST'. Please review the IP interface 'VZ_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (vz_axis_aclk) was removed from the interface 'VZ_AXIS_CLK'. Please review the IP interface 'VZ_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (y_axis_aresetn) was removed from the interface 'Y_AXIS_RST'. Please review the IP interface 'Y_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (y_axis_aclk) was removed from the interface 'Y_AXIS_CLK'. Please review the IP interface 'Y_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (vx_axis_aresetn) was removed from the interface 'VX_AXIS_RST'. Please review the IP interface 'VX_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (vx_axis_aclk) was removed from the interface 'VX_AXIS_CLK'. Please review the IP interface 'VX_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (x_axis_aresetn) was removed from the interface 'X_AXIS_RST'. Please review the IP interface 'X_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (x_axis_aclk) was removed from the interface 'X_AXIS_CLK'. Please review the IP interface 'X_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (vy_axis_aresetn) was removed from the interface 'VY_AXIS_RST'. Please review the IP interface 'VY_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (vy_axis_aclk) was removed from the interface 'VY_AXIS_CLK'. Please review the IP interface 'VY_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (c_axis_aresetn) was removed from the interface 'C_AXIS_RST'. Please review the IP interface 'C_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (c_axis_aclk) was removed from the interface 'C_AXIS_CLK'. Please review the IP interface 'C_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (z_axis_aresetn) was removed from the interface 'Z_AXIS_RST'. Please review the IP interface 'Z_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (z_axis_aclk) was removed from the interface 'Z_AXIS_CLK'. Please review the IP interface 'Z_AXIS_CLK'. INFO: [IP_Flow 19-3166] Bus Interface 'S00_AXI': References existing memory map 'S00_AXI'. set_property core_revision 2 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 current_project FP_Unit_Test report_ip_status -name ip_status current_project ultra96v2_oob delete_bd_objs [get_bd_cells application_to_accel_0] report_ip_status -name ip_status report_ip_status -name ip_status startgroup create_bd_cell -type ip -vlnv ecelrc:user:application_to_accel:1.0 application_to_accel_0 endgroup ipx::edit_ip_in_project -upgrade true -name application_to_accel_v1_0_project -directory /misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.tmp/application_to_accel_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/appl_to_accel_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/user_to_accelerator_1_0'. The path is contained within another repository. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 3 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'X_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Y_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'Z_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VX_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VY_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'VZ_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'C_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'DT_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0 CRITICAL WARNING: [IP_Flow 19-1681] Failed to reload user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0'. ''/misc/scratch/ahermez/Final_Project/ip_repo/application_to_accel_1_0' is not valid: Path is contained within another repository.' 0 report_ip_status -name ip_status upgrade_ip [get_ips ultra96v2_oob_application_to_accel_0_1] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd' INFO: [IP_Flow 19-3420] Updated ultra96v2_oob_application_to_accel_0_1 to use current project options Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/BASELINE_SP_2024/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips ultra96v2_oob_application_to_accel_0_1] -no_script -sync -force -quiet connect_bd_net [get_bd_pins force_sm_0/aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/dt_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/vz_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/y_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/s00_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/vx_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/x_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/vy_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/c_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/z_axis_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins application_to_accel_0/dt_axis_aresetn] [get_bd_pins force_sm_0/aresetn] connect_bd_net [get_bd_pins application_to_accel_0/vz_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/y_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/s00_axi_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/vx_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/x_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/vy_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/c_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_net [get_bd_pins application_to_accel_0/z_axis_aresetn] [get_bd_pins application_to_accel_0/dt_axis_aresetn] connect_bd_intf_net [get_bd_intf_pins application_to_accel_0/S00_AXI] -boundary_type upper [get_bd_intf_pins everything_except_the_accelerator/M00_AXI] save_bd_design WARNING: [BD 41-597] NET has no source Wrote : Wrote : report_ip_status -name ip_status close_project current_bd_design [get_bd_designs design_1] current_bd_design [get_bd_designs design_4] current_bd_design [get_bd_designs design_1] close_bd_design [get_bd_designs design_1] save_bd_design Wrote : Wrote : report_ip_status -name ip_status close_sim INFO: [Simtcl 6-16] Simulation closed exit INFO: [Common 17-206] Exiting Vivado at Fri May 3 09:03:53 2024...