#----------------------------------------------------------- # Vivado v2022.2 (64-bit) # SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 # Start of session at: Thu May 2 13:49:16 2024 # Process ID: 2347819 # Current directory: /misc/scratch/ahermez/Final_Project # Command line: vivado # Log file: /misc/scratch/ahermez/Final_Project/vivado.log # Journal file: /misc/scratch/ahermez/Final_Project/vivado.jou # Running On: kamek.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404276 MB #----------------------------------------------------------- start_gui WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available open_project /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. update_compile_order -fileset sources_1 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd} Reading block design file ... Adding component instance block -- ecelrc:user:Cascaded_FlipFlops:1.0 - Cascaded_FlipFlops_0 Successfully read diagram from block design file startgroup create_bd_port -dir I -from 2 -to 0 set_new connect_bd_net [get_bd_pins /Cascaded_FlipFlops_0/set_new] [get_bd_ports set_new] endgroup make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd] -top Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/synth/design_2.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/sim/design_2.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hdl/design_2_wrapper.v add_files -norecurse /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hdl/design_2_wrapper.v update_compile_order -fileset sources_1 set_property top design_2_wrapper [current_fileset] update_compile_order -fileset sources_1 create_fileset -simset sim_3 file mkdir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_3/new set_property SOURCE_SET sources_1 [get_filesets sim_3] close [ open /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_3/new/tb_cascaded_flipflops.v w ] add_files -fileset sim_3 /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_3/new/tb_cascaded_flipflops.v current_fileset -simset [ get_filesets sim_3 ] update_compile_order -fileset sim_3 set_property top tb_cascaded_flipflops [get_filesets sim_3] set_property top_lib xil_defaultlib [get_filesets sim_3] update_compile_order -fileset sim_3 set_property library xil_defaultlib [get_files] generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd] INFO: [BD 41-1662] The design 'design_2.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/synth/design_2.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/sim/design_2.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hdl/design_2_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block Cascaded_FlipFlops_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hw_handoff/design_2.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/synth/design_2.hwdef WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/ip/design_2_Cascaded_FlipFlops_0_0/design_2_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/synth/design_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/sim/design_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/design_2_ooc.xdc'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_3 ] Command: launch_simulation -simset sim_3 INFO: [Vivado 12-12493] Simulation top is 'tb_cascaded_flipflops' INFO: [Vivado 12-12490] The selected simulation model for 'design_2_Cascaded_FlipFlops_0_0' IP changed to 'rtl' from '', the simulation run directory will be deleted. WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_3' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_cascaded_flipflops' in fileset 'sim_3'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_3'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' xvlog --incr --relax -prj tb_cascaded_flipflops_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/ipshared/da25/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/ip/design_2_Cascaded_FlipFlops_0_0/sim/design_2_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/sim/design_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hdl/design_2_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_3/new/tb_cascaded_flipflops.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_cascaded_flipflops INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_cascaded_flipflops_behav xil_defaultlib.tb_cascaded_flipflops xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_cascaded_flipflops_behav xil_defaultlib.tb_cascaded_flipflops xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_2_Cascaded_FlipFlops_0_0 Compiling module xil_defaultlib.design_2 Compiling module xil_defaultlib.design_2_wrapper Compiling module xil_defaultlib.tb_cascaded_flipflops Compiling module xil_defaultlib.glbl Built simulation snapshot tb_cascaded_flipflops_behav INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_cascaded_flipflops_behav -key {Behavioral:sim_3:Functional:tb_cascaded_flipflops} -tclbatch {tb_cascaded_flipflops.tcl} -protoinst "protoinst_files/design_2.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_2.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/z_new_axis Time resolution is 1 ps source tb_cascaded_flipflops.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_cascaded_flipflops_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 7943.211 ; gain = 94.031 ; free physical = 366851 ; free virtual = 378574 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_3 ] Command: launch_simulation -simset sim_3 INFO: [Vivado 12-12493] Simulation top is 'tb_cascaded_flipflops' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_3' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_cascaded_flipflops' in fileset 'sim_3'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_3'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' xvlog --incr --relax -prj tb_cascaded_flipflops_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/ipshared/da25/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/ip/design_2_Cascaded_FlipFlops_0_0/sim/design_2_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/sim/design_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hdl/design_2_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_3/new/tb_cascaded_flipflops.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_cascaded_flipflops Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_cascaded_flipflops_behav xil_defaultlib.tb_cascaded_flipflops xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_cascaded_flipflops_behav xil_defaultlib.tb_cascaded_flipflops xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_2_Cascaded_FlipFlops_0_0 Compiling module xil_defaultlib.design_2 Compiling module xil_defaultlib.design_2_wrapper Compiling module xil_defaultlib.tb_cascaded_flipflops Compiling module xil_defaultlib.glbl Built simulation snapshot tb_cascaded_flipflops_behav INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_cascaded_flipflops_behav -key {Behavioral:sim_3:Functional:tb_cascaded_flipflops} -tclbatch {tb_cascaded_flipflops.tcl} -protoinst "protoinst_files/design_2.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_2.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/z_new_axis Time resolution is 1 ps source tb_cascaded_flipflops.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_cascaded_flipflops_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 8037.238 ; gain = 0.000 ; free physical = 366861 ; free virtual = 378585 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_3 ] Command: launch_simulation -simset sim_3 INFO: [Vivado 12-12493] Simulation top is 'tb_cascaded_flipflops' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_3' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_cascaded_flipflops' in fileset 'sim_3'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_3'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' xvlog --incr --relax -prj tb_cascaded_flipflops_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/ipshared/da25/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/ip/design_2_Cascaded_FlipFlops_0_0/sim/design_2_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_2/sim/design_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_2/hdl/design_2_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_2_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_3/new/tb_cascaded_flipflops.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_cascaded_flipflops Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_cascaded_flipflops_behav xil_defaultlib.tb_cascaded_flipflops xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_cascaded_flipflops_behav xil_defaultlib.tb_cascaded_flipflops xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_2_Cascaded_FlipFlops_0_0 Compiling module xil_defaultlib.design_2 Compiling module xil_defaultlib.design_2_wrapper Compiling module xil_defaultlib.tb_cascaded_flipflops Compiling module xil_defaultlib.glbl Built simulation snapshot tb_cascaded_flipflops_behav INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_3/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_cascaded_flipflops_behav -key {Behavioral:sim_3:Functional:tb_cascaded_flipflops} -tclbatch {tb_cascaded_flipflops.tcl} -protoinst "protoinst_files/design_2.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_2.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_cascaded_flipflops/uut/design_2_i//Cascaded_FlipFlops_0/z_new_axis Time resolution is 1 ps source tb_cascaded_flipflops.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_cascaded_flipflops_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8037.238 ; gain = 0.000 ; free physical = 366844 ; free virtual = 378568 create_peripheral ecelrc user 2x1_Mux 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:2x1_Mux:1.0] add_peripheral_interface S01_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:2x1_Mux:1.0] add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:2x1_Mux:1.0] generate_peripheral [ipx::find_open_core ecelrc:user:2x1_Mux:1.0] write_peripheral [ipx::find_open_core ecelrc:user:2x1_Mux:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. set_property ip_repo_paths /misc/scratch/ahermez/Final_Project/ip_repo [current_project] update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. ipx::edit_ip_in_project -upgrade true -name 2x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/2x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_M00_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S00_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S01_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0.v /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_M00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S01_AXIS.v} add_files -norecurse /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/Mux_v1_0.v update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/component.xml' ignored by IP packager. INFO: [Ipptcl 7-560] INFO: [Ipptcl 7-560] CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s01_axis_tlast s01_axis_tstrb) were removed from the interface 'S01_AXIS'. Please review the IP interface 'S01_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aresetn) was removed from the interface 'S01_AXIS_RST'. Please review the IP interface 'S01_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aclk) was removed from the interface 'S01_AXIS_CLK'. Please review the IP interface 'S01_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'. set_property name AXIS_2x1_Mux [ipx::current_core] set_property display_name AXIS_2x1_Mux_v1.0 [ipx::current_core] ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/component.xml' ignored by IP packager. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/component.xml' ignored by IP packager. INFO: [Ipptcl 7-560] INFO: [Ipptcl 7-560] close_project update_ip_catalog -delete_ip ecelrc:user:2x1_Mux:1.0 -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-881] Failed to delete file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S00_AXIS.v' because it doesn't exist. WARNING: [IP_Flow 19-881] Failed to delete file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_S01_AXIS.v' because it doesn't exist. WARNING: [IP_Flow 19-881] Failed to delete file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0_M00_AXIS.v' because it doesn't exist. WARNING: [IP_Flow 19-881] Failed to delete file '/misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0/hdl/2x1_Mux_v1_0.v' because it doesn't exist. INFO: [IP_Flow 19-1659] Deleted IP 'ecelrc:user:2x1_Mux:1.0' from repository '/misc/scratch/ahermez/Final_Project/ip_repo' at /misc/scratch/ahermez/Final_Project/ip_repo/2x1_Mux_1_0. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' create_peripheral ecelrc user AXIS_2x1_Mux 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_2x1_Mux:1.0] add_peripheral_interface S01_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_2x1_Mux:1.0] add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_2x1_Mux:1.0] generate_peripheral [ipx::find_open_core ecelrc:user:AXIS_2x1_Mux:1.0] write_peripheral [ipx::find_open_core ecelrc:user:AXIS_2x1_Mux:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. set_property ip_repo_paths /misc/scratch/ahermez/Final_Project/ip_repo [current_project] update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. ipx::edit_ip_in_project -upgrade true -name AXIS_2x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_2x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S01_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_M00_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S01_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_M00_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S00_AXIS.v] -no_script -reset -force -quiet remove_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S00_AXIS.v ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/hdl/AXIS_2x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/component.xml' ignored by IP packager. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s01_axis_tlast s01_axis_tstrb) were removed from the interface 'S01_AXIS'. Please review the IP interface 'S01_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aresetn) was removed from the interface 'S01_AXIS_RST'. Please review the IP interface 'S01_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aclk) was removed from the interface 'S01_AXIS_CLK'. Please review the IP interface 'S01_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'. set_property core_revision 2 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] set_property core_revision 3 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status create_peripheral ecelrc user AXIS_6x1_Mux 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] add_peripheral_interface S01_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] add_peripheral_interface S02_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] add_peripheral_interface S03_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] add_peripheral_interface S04_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] add_peripheral_interface S05_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] generate_peripheral [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] write_peripheral [ipx::find_open_core ecelrc:user:AXIS_6x1_Mux:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. set_property ip_repo_paths /misc/scratch/ahermez/Final_Project/ip_repo [current_project] update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. ipx::edit_ip_in_project -upgrade true -name AXIS_6x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_6x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_M00_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S00_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_M00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S00_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S01_AXIS.v] -no_script -reset -force -quiet remove_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S01_AXIS.v export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S02_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S03_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S02_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S03_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S04_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S05_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S04_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S05_AXIS.v} ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S04_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S05_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S04_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_S05_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/hdl/AXIS_6x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/component.xml' ignored by IP packager. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s01_axis_tlast s01_axis_tstrb) were removed from the interface 'S01_AXIS'. Please review the IP interface 'S01_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s02_axis_tlast s02_axis_tstrb) were removed from the interface 'S02_AXIS'. Please review the IP interface 'S02_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s03_axis_tlast s03_axis_tstrb) were removed from the interface 'S03_AXIS'. Please review the IP interface 'S03_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s04_axis_tlast s04_axis_tstrb) were removed from the interface 'S04_AXIS'. Please review the IP interface 'S04_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s05_axis_tlast s05_axis_tstrb) were removed from the interface 'S05_AXIS'. Please review the IP interface 'S05_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aresetn) was removed from the interface 'S01_AXIS_RST'. Please review the IP interface 'S01_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aclk) was removed from the interface 'S01_AXIS_CLK'. Please review the IP interface 'S01_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s05_axis_aresetn) was removed from the interface 'S05_AXIS_RST'. Please review the IP interface 'S05_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s05_axis_aclk) was removed from the interface 'S05_AXIS_CLK'. Please review the IP interface 'S05_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s04_axis_aresetn) was removed from the interface 'S04_AXIS_RST'. Please review the IP interface 'S04_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s04_axis_aclk) was removed from the interface 'S04_AXIS_CLK'. Please review the IP interface 'S04_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s03_axis_aresetn) was removed from the interface 'S03_AXIS_RST'. Please review the IP interface 'S03_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s03_axis_aclk) was removed from the interface 'S03_AXIS_CLK'. Please review the IP interface 'S03_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aresetn) was removed from the interface 'S02_AXIS_RST'. Please review the IP interface 'S02_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aclk) was removed from the interface 'S02_AXIS_CLK'. Please review the IP interface 'S02_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'. set_property core_revision 2 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S02_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S03_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S04_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S05_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' create_peripheral ecelrc user AXIS_3x1_Mux 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_3x1_Mux:1.0] add_peripheral_interface S01_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_3x1_Mux:1.0] add_peripheral_interface S02_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_3x1_Mux:1.0] add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_3x1_Mux:1.0] generate_peripheral [ipx::find_open_core ecelrc:user:AXIS_3x1_Mux:1.0] write_peripheral [ipx::find_open_core ecelrc:user:AXIS_3x1_Mux:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. set_property ip_repo_paths /misc/scratch/ahermez/Final_Project/ip_repo [current_project] update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. ipx::edit_ip_in_project -upgrade true -name AXIS_3x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_3x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_M00_AXIS.v] -no_script -reset -force -quiet remove_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_M00_AXIS.v export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S00_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S01_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S01_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S02_AXIS.v] -no_script -reset -force -quiet remove_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S02_AXIS.v ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/hdl/AXIS_3x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/component.xml' ignored by IP packager. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s01_axis_tlast s01_axis_tstrb) were removed from the interface 'S01_AXIS'. Please review the IP interface 'S01_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s02_axis_tlast s02_axis_tstrb) were removed from the interface 'S02_AXIS'. Please review the IP interface 'S02_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aresetn) was removed from the interface 'S02_AXIS_RST'. Please review the IP interface 'S02_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aclk) was removed from the interface 'S02_AXIS_CLK'. Please review the IP interface 'S02_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aresetn) was removed from the interface 'S01_AXIS_RST'. Please review the IP interface 'S01_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aclk) was removed from the interface 'S01_AXIS_CLK'. Please review the IP interface 'S01_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'. set_property core_revision 2 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S02_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' ipx::edit_ip_in_project -upgrade true -name AXIS_3x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_3x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 3 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S02_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' create_peripheral ecelrc user AXIS_4x1_Mux 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] add_peripheral_interface S01_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] add_peripheral_interface S02_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] add_peripheral_interface S03_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] generate_peripheral [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] write_peripheral [ipx::find_open_core ecelrc:user:AXIS_4x1_Mux:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. set_property ip_repo_paths /misc/scratch/ahermez/Final_Project/ip_repo [current_project] update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. ipx::edit_ip_in_project -upgrade true -name AXIS_4x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_4x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_M00_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S00_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_M00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S00_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S02_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S01_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S02_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S01_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S03_AXIS.v] -no_script -reset -force -quiet remove_files /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S03_AXIS.v ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_S03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/hdl/AXIS_4x1_Mux_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_4x1_Mux_1_0/component.xml' ignored by IP packager. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s01_axis_tlast s01_axis_tstrb) were removed from the interface 'S01_AXIS'. Please review the IP interface 'S01_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s02_axis_tlast s02_axis_tstrb) were removed from the interface 'S02_AXIS'. Please review the IP interface 'S02_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s03_axis_tlast s03_axis_tstrb) were removed from the interface 'S03_AXIS'. Please review the IP interface 'S03_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aresetn) was removed from the interface 'S02_AXIS_RST'. Please review the IP interface 'S02_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aclk) was removed from the interface 'S02_AXIS_CLK'. Please review the IP interface 'S02_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s03_axis_aresetn) was removed from the interface 'S03_AXIS_RST'. Please review the IP interface 'S03_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s03_axis_aclk) was removed from the interface 'S03_AXIS_CLK'. Please review the IP interface 'S03_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aresetn) was removed from the interface 'S01_AXIS_RST'. Please review the IP interface 'S01_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aclk) was removed from the interface 'S01_AXIS_CLK'. Please review the IP interface 'S01_AXIS_CLK'. set_property core_revision 2 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S02_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S03_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' ipx::edit_ip_in_project -upgrade true -name Fused_2x1Mux_FPAdder_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Fused_2x1Mux_FPAdder_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Fused_2x1Mux_FPAdder_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 7 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' create_peripheral ecelrc user Crossbar_Bypass_1x2 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:Crossbar_Bypass_1x2:1.0] add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:Crossbar_Bypass_1x2:1.0] add_peripheral_interface M01_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:Crossbar_Bypass_1x2:1.0] generate_peripheral [ipx::find_open_core ecelrc:user:Crossbar_Bypass_1x2:1.0] write_peripheral [ipx::find_open_core ecelrc:user:Crossbar_Bypass_1x2:1.0] set_property ip_repo_paths {/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project] update_ip_catalog -rebuild INFO: [IP_Flow 19-234] Refreshing IP repositories WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0'. The path is contained within another repository. WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. set_property ip_repo_paths /misc/scratch/ahermez/Final_Project/ip_repo [current_project] update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. ipx::edit_ip_in_project -upgrade true -name Crossbar_Bypass_1x2_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Crossbar_Bypass_1x2_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 ipx::merge_project_changes files [ipx::current_core] WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M00_AXIS.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M01_AXIS.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_S00_AXIS.v'. WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/component.xml' ignored by IP packager. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M00_AXIS.v] -no_script -reset -force -quiet export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M01_AXIS.v] -no_script -reset -force -quiet remove_files {/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_M01_AXIS.v} export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_S00_AXIS.v] -no_script -reset -force -quiet remove_files /misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/hdl/Crossbar_Bypass_1x2_v1_0_S00_AXIS.v ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/Crossbar_Bypass_1x2_1_0/component.xml' ignored by IP packager. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'. CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m01_axis_tlast m01_axis_tstrb) were removed from the interface 'M01_AXIS'. Please review the IP interface 'M01_AXIS'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m01_axis_aresetn) was removed from the interface 'M01_AXIS_RST'. Please review the IP interface 'M01_AXIS_RST'. CRITICAL WARNING: [IP_Flow 19-4834] IP port (m01_axis_aclk) was removed from the interface 'M01_AXIS_CLK'. Please review the IP interface 'M01_AXIS_CLK'. set_property core_revision 2 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status create_bd_design "design_3" Wrote : update_compile_order -fileset sources_1 startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 endgroup set_property -dict [list \ CONFIG.Add_Sub_Value {Add} \ CONFIG.C_Latency {0} \ CONFIG.Flow_Control {NonBlocking} \ CONFIG.Has_RESULT_TREADY {false} \ CONFIG.Maximum_Latency {false} \ ] [get_bd_cells floating_point_0] set_property location {1 174 -76} [get_bd_cells floating_point_0] set_property name non_blocking_fpadder [get_bd_cells floating_point_0] set_property location {1 185 -147} [get_bd_cells non_blocking_fpadder] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_6x1_Mux:1.0 AXIS_6x1_Mux_0 endgroup set_property location {1 12 -242} [get_bd_cells AXIS_6x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/M00_AXIS] [get_bd_intf_pins non_blocking_fpadder/S_AXIS_A] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_2x1_Mux:1.0 AXIS_2x1_Mux_0 endgroup set_property location {3.5 890 -150} [get_bd_cells AXIS_2x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins non_blocking_fpadder/M_AXIS_RESULT] [get_bd_intf_pins AXIS_2x1_Mux_0/S00_AXIS] set_property location {3 880 -78} [get_bd_cells AXIS_2x1_Mux_0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0 endgroup set_property location {2 352 -56} [get_bd_cells Crossbar_Bypass_1x2_0] startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 external_data set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS]] [get_bd_intf_ports external_data] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS] [get_bd_intf_ports external_data] endgroup connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M00_AXIS] [get_bd_intf_pins non_blocking_fpadder/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_0/S01_AXIS] set_property location {1 380 -313} [get_bd_cells AXIS_6x1_Mux_0] startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_6x1_Mux_0/S00_AXIS]] [get_bd_intf_ports S00_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/S00_AXIS] [get_bd_intf_ports S00_AXIS] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S01_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_6x1_Mux_0/S01_AXIS]] [get_bd_intf_ports S01_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/S01_AXIS] [get_bd_intf_ports S01_AXIS] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S02_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_6x1_Mux_0/S02_AXIS]] [get_bd_intf_ports S02_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/S02_AXIS] [get_bd_intf_ports S02_AXIS] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S03_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_6x1_Mux_0/S03_AXIS]] [get_bd_intf_ports S03_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/S03_AXIS] [get_bd_intf_ports S03_AXIS] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S04_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_6x1_Mux_0/S04_AXIS]] [get_bd_intf_ports S04_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/S04_AXIS] [get_bd_intf_ports S04_AXIS] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S05_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_6x1_Mux_0/S05_AXIS]] [get_bd_intf_ports S05_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/S05_AXIS] [get_bd_intf_ports S05_AXIS] endgroup set_property location {-15 -345} [get_bd_intf_ports S01_AXIS] set_property location {-5 -329} [get_bd_intf_ports S02_AXIS] set_property location {-13 -373} [get_bd_intf_ports S00_AXIS] startgroup create_bd_port -dir I -from 2 -to 0 select6x1 connect_bd_net [get_bd_pins /AXIS_6x1_Mux_0/select] [get_bd_ports select6x1] endgroup set_property location {-12 -247} [get_bd_ports select6x1] set_property location {-10 -61} [get_bd_intf_ports external_data] startgroup create_bd_port -dir I select2x1 connect_bd_net [get_bd_pins /AXIS_2x1_Mux_0/select] [get_bd_ports select2x1] endgroup set_property location {-11 -17} [get_bd_ports select2x1] startgroup create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M00_AXIS connect_bd_intf_net [get_bd_intf_pins AXIS_2x1_Mux_0/M00_AXIS] [get_bd_intf_ports M00_AXIS] endgroup save_bd_design Wrote : Wrote : current_bd_design [get_bd_designs design_2] close_bd_design [get_bd_designs design_2] Wrote : make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -top CRITICAL WARNING: [BD 41-1367] The port name 'select' of cell '/AXIS_6x1_Mux_0' is a reserved keyword in a Hardware Description Language. Please consider renaming the port. CRITICAL WARNING: [BD 41-1367] The port name 'select' of cell '/AXIS_2x1_Mux_0' is a reserved keyword in a Hardware Description Language. Please consider renaming the port. CRITICAL WARNING: [BD 41-968] AXI interface port /external_data is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S01_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S02_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S03_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S04_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S05_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /M00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/S_AXIS_A is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/S_AXIS_B is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/M_AXIS_RESULT is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v add_files -norecurse /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v update_compile_order -fileset sources_1 set_property top design_3_wrapper [current_fileset] update_compile_order -fileset sources_1 set_property name result_AXIS [get_bd_intf_ports M00_AXIS] set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {AXIS_6x1_Mux_0_M00_AXIS}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M00_AXIS}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {non_blocking_fpadder_M_AXIS_RESULT}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M01_AXIS}] true create_fileset -simset sim_4 file mkdir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new set_property SOURCE_SET sources_1 [get_filesets sim_4] close [ open /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v w ] add_files -fileset sim_4 /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v current_fileset -simset [ get_filesets sim_4 ] update_compile_order -fileset sim_4 set_property top tb_mux_adder [get_filesets sim_4] set_property top_lib xil_defaultlib [get_filesets sim_4] update_compile_order -fileset sim_4 update_compile_order -fileset sim_4 set_property top tb_mux_adder [get_filesets sim_4] set_property top_lib xil_defaultlib [get_filesets sim_4] update_compile_order -fileset sim_4 save_bd_design Wrote : Wrote : reset_simulation -simset sim_4 -mode behavioral set_property library xil_defaultlib [get_files] generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] CRITICAL WARNING: [BD 41-1367] The port name 'select' of cell '/AXIS_6x1_Mux_0' is a reserved keyword in a Hardware Description Language. Please consider renaming the port. CRITICAL WARNING: [BD 41-1367] The port name 'select' of cell '/AXIS_2x1_Mux_0' is a reserved keyword in a Hardware Description Language. Please consider renaming the port. CRITICAL WARNING: [BD 41-968] AXI interface port /external_data is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S01_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S02_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S03_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S04_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S05_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /result_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/S_AXIS_A is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/S_AXIS_B is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/M_AXIS_RESULT is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block non_blocking_fpadder . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_6x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_2x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Crossbar_Bypass_1x2_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S_AXIS_A could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /non_blocking_fpadder WARNING: [BD 41-2265] Clock pin for protocol instance pin S_AXIS_B could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /non_blocking_fpadder WARNING: [BD 41-2265] Clock pin for protocol instance pin M_AXIS_RESULT could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /non_blocking_fpadder WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_floating_point_0_0/design_3_floating_point_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/design_3_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/design_3_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/design_3_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3_ooc.xdc'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_4 ] Command: launch_simulation -simset sim_4 INFO: [Vivado 12-12493] Simulation top is 'tb_mux_adder' INFO: [Vivado 12-12490] The selected simulation model for 'design_3_AXIS_2x1_Mux_0_0' IP changed to 'rtl' from '', the simulation run directory will be deleted. WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_4' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_mux_adder' in fileset 'sim_4'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_4'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xvlog --incr --relax -prj tb_mux_adder_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_floating_point_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/8f2e/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/7d98/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/sim/design_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_mux_adder INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_mux_adder_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tvalid' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:77] ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tready' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:76] ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tdata' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:75] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 8985.945 ; gain = 0.000 ; free physical = 365704 ; free virtual = 377489 ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} ipx::edit_ip_in_project -upgrade true -name AXIS_6x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_6x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_6x1_Mux_1_0/component.xml' ignored by IP packager. set_property core_revision 3 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S02_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S03_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S04_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S05_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' ipx::edit_ip_in_project -upgrade true -name AXIS_2x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_2x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_2x1_Mux_1_0/component.xml' ignored by IP packager. set_property core_revision 4 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_3_AXIS_2x1_Mux_0_0 design_3_AXIS_6x1_Mux_0_0}] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd' INFO: [IP_Flow 19-3422] Upgraded design_3_AXIS_2x1_Mux_0_0 (AXIS_2x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select2x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_3_AXIS_2x1_Mux_0_0'. These changes may impact your design. CRITICAL WARNING: [BD 41-1167] The pin 'select' is not found on the upgraded version of the cell '/AXIS_2x1_Mux_0'. Its connection to the net 'select2x1_1' has been removed. INFO: [IP_Flow 19-3422] Upgraded design_3_AXIS_6x1_Mux_0_0 (AXIS_6x1_Mux_v1.0 1.0) from revision 2 to revision 3 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select6x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_3_AXIS_6x1_Mux_0_0'. These changes may impact your design. CRITICAL WARNING: [BD 41-1167] The pin 'select' is not found on the upgraded version of the cell '/AXIS_6x1_Mux_0'. Its connection to the net 'select6x1_1' has been removed. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_3_AXIS_2x1_Mux_0_0' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_3_AXIS_6x1_Mux_0_0' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips {design_3_AXIS_2x1_Mux_0_0 design_3_AXIS_6x1_Mux_0_0}] -no_script -sync -force -quiet set_property location {-19 -246} [get_bd_ports select6x1] connect_bd_net [get_bd_ports select6x1] [get_bd_pins AXIS_6x1_Mux_0/select6x1] connect_bd_net [get_bd_ports select2x1] [get_bd_pins AXIS_2x1_Mux_0/select2x1] save_bd_design Wrote : Wrote : report_ip_status -name ip_status set_property library xil_defaultlib [get_files] reset_simulation -simset sim_4 -mode behavioral INFO: [Vivado 12-2266] Removing simulation data... INFO: [Vivado 12-2267] Reset complete generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] CRITICAL WARNING: [BD 41-968] AXI interface port /external_data is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S01_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S02_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S03_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S04_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S05_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /result_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/S_AXIS_A is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/S_AXIS_B is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /non_blocking_fpadder/M_AXIS_RESULT is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_6x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_2x1_Mux_0 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S_AXIS_A could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /non_blocking_fpadder WARNING: [BD 41-2265] Clock pin for protocol instance pin S_AXIS_B could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /non_blocking_fpadder WARNING: [BD 41-2265] Clock pin for protocol instance pin M_AXIS_RESULT could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /non_blocking_fpadder WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_floating_point_0_0/design_3_floating_point_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/design_3_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/design_3_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/design_3_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_4 ] Command: launch_simulation -simset sim_4 INFO: [Vivado 12-12493] Simulation top is 'tb_mux_adder' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_4' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_mux_adder' in fileset 'sim_4'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_4'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xvlog --incr --relax -prj tb_mux_adder_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_floating_point_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/sim/design_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_mux_adder INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_mux_adder_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tvalid' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:77] ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tready' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:76] ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tdata' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:75] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 9265.086 ; gain = 0.000 ; free physical = 366321 ; free virtual = 378098 ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} startgroup set_property -dict [list \ CONFIG.Axi_Optimize_Goal {Resources} \ CONFIG.C_Latency {1} \ CONFIG.Flow_Control {Blocking} \ CONFIG.Has_RESULT_TREADY {true} \ ] [get_bd_cells non_blocking_fpadder] endgroup startgroup create_bd_port -dir I -type clk -freq_hz 100000000 aclk connect_bd_net [get_bd_pins /non_blocking_fpadder/aclk] [get_bd_ports aclk] endgroup set_property name blocking_fpadder [get_bd_cells non_blocking_fpadder] open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} save_bd_design Wrote : Wrote : make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -top CRITICAL WARNING: [BD 41-968] AXI interface port /external_data is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S01_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S02_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S03_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S04_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S05_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /result_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v set_property library xil_defaultlib [get_files] reset_simulation -simset sim_4 -mode behavioral INFO: [Vivado 12-2266] Removing simulation data... INFO: [Vivado 12-2267] Reset complete generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] INFO: [BD 41-1662] The design 'design_3.bd' is already validated. Therefore parameter propagation will not be re-run. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block blocking_fpadder . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_floating_point_0_0/design_3_floating_point_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/design_3_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/design_3_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/design_3_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_4 ] Command: launch_simulation -simset sim_4 INFO: [Vivado 12-12493] Simulation top is 'tb_mux_adder' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_4' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_mux_adder' in fileset 'sim_4'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_4'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xvlog --incr --relax -prj tb_mux_adder_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_floating_point_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/sim/design_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_mux_adder INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_mux_adder_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tvalid' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:84] ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tready' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:83] ERROR: [VRFC 10-3180] cannot find port 'M00_AXIS_tdata' on this module [/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v:82] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 9369.129 ; gain = 0.000 ; free physical = 366300 ; free virtual = 378077 ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} delete_bd_objs [get_bd_intf_nets AXIS_2x1_Mux_0_M00_AXIS] [get_bd_intf_ports result_AXIS] startgroup create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M00_AXIS connect_bd_intf_net [get_bd_intf_pins AXIS_2x1_Mux_0/M00_AXIS] [get_bd_intf_ports M00_AXIS] endgroup save_bd_design Wrote : Wrote : report_ip_status -name ip_status make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -top CRITICAL WARNING: [BD 41-968] AXI interface port /external_data is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S01_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S02_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S03_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S04_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S05_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /M00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v reset_simulation -simset sim_4 -mode behavioral INFO: [Vivado 12-2266] Removing simulation data... INFO: [Vivado 12-2267] Reset complete generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] INFO: [BD 41-1662] The design 'design_3.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_floating_point_0_0/design_3_floating_point_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/design_3_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/design_3_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/design_3_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_4 ] Command: launch_simulation -simset sim_4 INFO: [Vivado 12-12493] Simulation top is 'tb_mux_adder' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_4' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_mux_adder' in fileset 'sim_4'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_4'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xvlog --incr --relax -prj tb_mux_adder_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_floating_point_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/sim/design_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_mux_adder INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_mux_adder_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling package unisim.vcomponents Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_3_AXIS_2x1_Mux_0_0 Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_3_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_3_Crossbar_Bypass_1x2_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_3_floating_point_0_0 Compiling module xil_defaultlib.design_3 Compiling module xil_defaultlib.design_3_wrapper Compiling module xil_defaultlib.tb_mux_adder Compiling module xil_defaultlib.glbl Built simulation snapshot tb_mux_adder_behav execute_script: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 9549.227 ; gain = 0.000 ; free physical = 365880 ; free virtual = 377676 INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_mux_adder_behav -key {Behavioral:sim_4:Functional:tb_mux_adder} -tclbatch {tb_mux_adder.tcl} -protoinst "protoinst_files/design_3.protoinst" -protoinst "protoinst_files/design_2.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/S_AXIS_B INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_2.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_2.protoinst for the following reason(s): There are no instances of module "design_2" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing Time resolution is 1 ps source tb_mux_adder.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_mux_adder_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 9872.188 ; gain = 322.961 ; free physical = 365862 ; free virtual = 377655 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {AXIS_6x1_Mux_0_M00_AXIS}] set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M01_AXIS}] set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {non_blocking_fpadder_M_AXIS_RESULT}] save_bd_design Wrote : Wrote : close_sim INFO: [Simtcl 6-16] Simulation closed generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] INFO: [BD 41-1662] The design 'design_3.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_2x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_floating_point_0_0/design_3_floating_point_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/design_3_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/design_3_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/design_3_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hw_handoff/design_3.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/design_3.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/synth/design_3.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/sim/design_3.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v'. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_4 ] Command: launch_simulation -simset sim_4 INFO: [Vivado 12-12493] Simulation top is 'tb_mux_adder' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_4' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_mux_adder' in fileset 'sim_4'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_4'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xvlog --incr --relax -prj tb_mux_adder_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_floating_point_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/sim/design_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_mux_adder xvhdl --incr --relax -prj tb_mux_adder_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling package unisim.vcomponents Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_3_AXIS_2x1_Mux_0_0 Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_3_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_3_Crossbar_Bypass_1x2_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_3_floating_point_0_0 Compiling module xil_defaultlib.design_3 Compiling module xil_defaultlib.design_3_wrapper Compiling module xil_defaultlib.tb_mux_adder Compiling module xil_defaultlib.glbl Built simulation snapshot tb_mux_adder_behav execute_script: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 9872.188 ; gain = 0.000 ; free physical = 366278 ; free virtual = 378065 INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_mux_adder_behav -key {Behavioral:sim_4:Functional:tb_mux_adder} -tclbatch {tb_mux_adder.tcl} -protoinst "protoinst_files/design_3.protoinst" -protoinst "protoinst_files/design_2.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/S_AXIS_B INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_2.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_2.protoinst for the following reason(s): There are no instances of module "design_2" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing Time resolution is 1 ps source tb_mux_adder.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_mux_adder_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 9872.188 ; gain = 0.000 ; free physical = 366270 ; free virtual = 378055 current_sim simulation_3 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_4 ] Command: launch_simulation -simset sim_4 INFO: [Vivado 12-12493] Simulation top is 'tb_mux_adder' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_4' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_mux_adder' in fileset 'sim_4'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_4'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xvlog --incr --relax -prj tb_mux_adder_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_floating_point_0_0/sim/design_3_floating_point_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_floating_point_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_6x1_Mux_0_0/sim/design_3_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_AXIS_2x1_Mux_0_0/sim/design_3_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/ip/design_3_Crossbar_Bypass_1x2_0_0/sim/design_3_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_3/sim/design_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_3/hdl/design_3_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_3_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_4/new/tb_mux_adder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_mux_adder xvhdl --incr --relax -prj tb_mux_adder_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_mux_adder_behav xil_defaultlib.tb_mux_adder xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling package unisim.vcomponents Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_3_AXIS_2x1_Mux_0_0 Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_3_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_3_Crossbar_Bypass_1x2_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_3_floating_point_0_0 Compiling module xil_defaultlib.design_3 Compiling module xil_defaultlib.design_3_wrapper Compiling module xil_defaultlib.tb_mux_adder Compiling module xil_defaultlib.glbl Built simulation snapshot tb_mux_adder_behav execute_script: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 9872.188 ; gain = 0.000 ; free physical = 366266 ; free virtual = 378053 INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_4/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_mux_adder_behav -key {Behavioral:sim_4:Functional:tb_mux_adder} -tclbatch {tb_mux_adder.tcl} -protoinst "protoinst_files/design_3.protoinst" -protoinst "protoinst_files/design_2.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_mux_adder/uut/design_3_i//blocking_fpadder/S_AXIS_B INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_2.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_2.protoinst for the following reason(s): There are no instances of module "design_2" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_mux_adder/uut/design_3_i//Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing Time resolution is 1 ps source tb_mux_adder.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_mux_adder_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 9872.188 ; gain = 0.000 ; free physical = 366230 ; free virtual = 378015 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_3/design_3.bd} create_bd_design "design_4" Wrote : startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 endgroup set_property -dict [list \ CONFIG.Add_Sub_Value {Add} \ CONFIG.Axi_Optimize_Goal {Resources} \ CONFIG.C_Latency {2} \ CONFIG.C_Mult_Usage {Medium_Usage} \ CONFIG.C_Rate {1} \ CONFIG.C_Result_Exponent_Width {8} \ CONFIG.C_Result_Fraction_Width {24} \ CONFIG.Has_ARESETn {true} \ CONFIG.Has_A_TLAST {true} \ CONFIG.Maximum_Latency {false} \ CONFIG.Operation_Type {Accumulator} \ CONFIG.RESULT_TLAST_Behv {Pass_A_TLAST} \ CONFIG.Result_Precision_Type {Single} \ ] [get_bd_cells floating_point_0] update_compile_order -fileset sources_1 ipx::edit_ip_in_project -upgrade true -name Cascaded_FlipFlops_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Cascaded_FlipFlops_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Cascaded_FlipFlops_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 4 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' ipx::edit_ip_in_project -upgrade true -name force_sm_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/force_sm_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/force_sm_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 8 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' delete_bd_objs [get_bd_cells floating_point_0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Cascaded_FlipFlops:1.0 Cascaded_FlipFlops_0 endgroup set_property location {1 57 -302} [get_bd_cells Cascaded_FlipFlops_0] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_3x1_Mux:1.0 AXIS_3x1_Mux_0 endgroup set_property location {1 76 -556} [get_bd_cells AXIS_3x1_Mux_0] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_0}] set_property location {1 132 -404} [get_bd_cells AXIS_3x1_Mux_1] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_0}] set_property location {1 122 -243} [get_bd_cells AXIS_3x1_Mux_2] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_0}] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_0}] set_property location {2 375 -545} [get_bd_cells AXIS_3x1_Mux_4] copy_bd_objs / [get_bd_cells {AXIS_3x1_Mux_0}] group_bd_cells AXIS_3x1_Muxes [get_bd_cells AXIS_3x1_Mux_0] [get_bd_cells AXIS_3x1_Mux_1] [get_bd_cells AXIS_3x1_Mux_2] [get_bd_cells AXIS_3x1_Mux_3] [get_bd_cells AXIS_3x1_Mux_4] [get_bd_cells AXIS_3x1_Mux_5] set_property screensize {112 294} [get_bd_cells AXIS_3x1_Muxes] set_property screensize {173 658} [get_bd_cells AXIS_3x1_Muxes] set_property screensize {142 174} [get_bd_cells AXIS_3x1_Muxes] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/x_new_axis] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/y_new_axis] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/z_new_axis] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vx_new_axis] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/vy_new_axis] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS] [get_bd_intf_pins Cascaded_FlipFlops_0/vz_new_axis] ipx::edit_ip_in_project -upgrade true -name AXIS_3x1_Mux_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/AXIS_3x1_Mux_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 ipx::merge_project_changes hdl_parameters [ipx::current_core] WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/AXIS_3x1_Mux_1_0/component.xml' ignored by IP packager. set_property core_revision 4 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S01_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'S02_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status upgrade_ip [get_ips {design_1_force_sm_0_0 design_2_Cascaded_FlipFlops_0_0 design_4_AXIS_3x1_Mux_0_5 design_4_AXIS_3x1_Mux_0_2 design_4_AXIS_3x1_Mux_0_0 design_4_AXIS_3x1_Mux_0_1 design_4_AXIS_3x1_Mux_0_4 design_4_AXIS_3x1_Mux_0_3}] -log ip_upgrade.log Reading block design file ... Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_1 Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_2 Adding component instance block -- ecelrc:user:force_sm:1.0 - force_sm_0 Successfully read diagram from block design file Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_1/design_1.bd' INFO: [IP_Flow 19-3422] Upgraded design_1_force_sm_0_0 (force_sm_v1.0 1.0) from revision 7 to revision 8 Wrote : Wrote : Reading block design file ... Adding component instance block -- ecelrc:user:Cascaded_FlipFlops:1.0 - Cascaded_FlipFlops_0 Successfully read diagram from block design file Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd' INFO: [IP_Flow 19-3422] Upgraded design_2_Cascaded_FlipFlops_0_0 (Cascaded_FlipFlops_v1.0 1.0) from revision 3 to revision 4 Wrote : Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_AXIS_3x1_Mux_0_0 (AXIS_3x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select3x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_4_AXIS_3x1_Mux_0_0'. These changes may impact your design. INFO: [IP_Flow 19-3422] Upgraded design_4_AXIS_3x1_Mux_0_1 (AXIS_3x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select3x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_4_AXIS_3x1_Mux_0_1'. These changes may impact your design. INFO: [IP_Flow 19-3422] Upgraded design_4_AXIS_3x1_Mux_0_2 (AXIS_3x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select3x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_4_AXIS_3x1_Mux_0_2'. These changes may impact your design. INFO: [IP_Flow 19-3422] Upgraded design_4_AXIS_3x1_Mux_0_3 (AXIS_3x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select3x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_4_AXIS_3x1_Mux_0_3'. These changes may impact your design. INFO: [IP_Flow 19-3422] Upgraded design_4_AXIS_3x1_Mux_0_4 (AXIS_3x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select3x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_4_AXIS_3x1_Mux_0_4'. These changes may impact your design. INFO: [IP_Flow 19-3422] Upgraded design_4_AXIS_3x1_Mux_0_5 (AXIS_3x1_Mux_v1.0 1.0) from revision 3 to revision 4 WARNING: [IP_Flow 19-4700] Upgrade has removed port 'select' WARNING: [IP_Flow 19-4698] Upgrade has added port 'select3x1' WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'design_4_AXIS_3x1_Mux_0_5'. These changes may impact your design. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_4_AXIS_3x1_Mux_0_0' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_4_AXIS_3x1_Mux_0_1' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_4_AXIS_3x1_Mux_0_2' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_4_AXIS_3x1_Mux_0_3' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_4_AXIS_3x1_Mux_0_4' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'design_4_AXIS_3x1_Mux_0_5' has identified issues that may require user intervention. Please review the upgrade log '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log', and verify that the upgraded IP is correctly configured. Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. upgrade_ip: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 10207.535 ; gain = 0.000 ; free physical = 364942 ; free virtual = 376944 export_ip_user_files -of_objects [get_ips {design_1_force_sm_0_0 design_2_Cascaded_FlipFlops_0_0 design_4_AXIS_3x1_Mux_0_5 design_4_AXIS_3x1_Mux_0_2 design_4_AXIS_3x1_Mux_0_0 design_4_AXIS_3x1_Mux_0_1 design_4_AXIS_3x1_Mux_0_4 design_4_AXIS_3x1_Mux_0_3}] -no_script -sync -force -quiet current_bd_design [get_bd_designs design_3] close_bd_design [get_bd_designs design_3] Wrote : close_bd_design [get_bd_designs design_1] close_bd_design [get_bd_designs design_2] report_ip_status -name ip_status open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0 endgroup set_property location {1 -16 -358} [get_bd_cells Crossbar_Bypass_1x2_0] set_property location {1 25 -489} [get_bd_cells Crossbar_Bypass_1x2_0] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] set_property location {1 37 -299} [get_bd_cells Crossbar_Bypass_1x2_1] set_property location {1 21 -659} [get_bd_cells Crossbar_Bypass_1x2_0] set_property location {1 26 -547} [get_bd_cells Crossbar_Bypass_1x2_1] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_1/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_2/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_2/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_3/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_3/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_4/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_4/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_5/S00_AXIS] delete_bd_objs [get_bd_intf_nets Crossbar_Bypass_1x2_4_M00_AXIS] [get_bd_cells Crossbar_Bypass_1x2_5] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_2/M01_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_3/M01_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_4/M00_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_4/M01_AXIS] startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS]] [get_bd_intf_ports S00_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS] [get_bd_intf_ports S00_AXIS] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS_1 set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS]] [get_bd_intf_ports S00_AXIS_1] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS] [get_bd_intf_ports S00_AXIS_1] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS_2 set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS]] [get_bd_intf_ports S00_AXIS_2] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS] [get_bd_intf_ports S00_AXIS_2] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS_3 set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS]] [get_bd_intf_ports S00_AXIS_3] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS] [get_bd_intf_ports S00_AXIS_3] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS_4 set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS]] [get_bd_intf_ports S00_AXIS_4] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS] [get_bd_intf_ports S00_AXIS_4] endgroup startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S00_AXIS_5 set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS]] [get_bd_intf_ports S00_AXIS_5] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS] [get_bd_intf_ports S00_AXIS_5] endgroup group_bd_cells add_result [get_bd_cells Crossbar_Bypass_1x2_0] [get_bd_cells Crossbar_Bypass_1x2_1] [get_bd_cells Crossbar_Bypass_1x2_2] [get_bd_cells Crossbar_Bypass_1x2_3] [get_bd_cells Crossbar_Bypass_1x2_4] set_property location {1 97 -389} [get_bd_cells add_result] set_property location {-178 -260} [get_bd_intf_ports S00_AXIS] set_property location {-192 -214} [get_bd_intf_ports S00_AXIS_2] set_property location {-187 -175} [get_bd_intf_ports S00_AXIS_3] set_property location {-206 -119} [get_bd_intf_ports S00_AXIS_4] set_property location {-197 -665} [get_bd_intf_ports S00_AXIS_4] set_property location {-174 -132} [get_bd_intf_ports S00_AXIS_4] set_property location {-202 -98} [get_bd_intf_ports S00_AXIS_5] set_property location {1 40 -518} [get_bd_cells add_result] set_property location {-188 -294} [get_bd_intf_ports S00_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_2x1_Mux:1.0 AXIS_2x1_Mux_0 endgroup set_property location {2 215 -11} [get_bd_cells AXIS_2x1_Mux_0] set_property location {1 200 19} [get_bd_cells AXIS_2x1_Mux_0] startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 endgroup set_property -dict [list \ CONFIG.Add_Sub_Value {Add} \ CONFIG.C_Latency {1} \ CONFIG.Maximum_Latency {false} \ ] [get_bd_cells floating_point_0] set_property location {1 86 18} [get_bd_cells floating_point_0] connect_bd_intf_net [get_bd_intf_pins floating_point_0/M_AXIS_RESULT] [get_bd_intf_pins AXIS_2x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_2x1_Mux_0/M00_AXIS] [get_bd_intf_pins add_result/Crossbar_Bypass_1x2_0/S00_AXIS] set_property location {1 29 45} [get_bd_cells floating_point_0] copy_bd_objs / [get_bd_cells {add_result}] delete_bd_objs [get_bd_cells add_result1] delete_bd_objs [get_bd_intf_nets S00_AXIS_1] delete_bd_objs [get_bd_intf_nets S00_AXIS_1_1] delete_bd_objs [get_bd_intf_nets S00_AXIS_2_1] delete_bd_objs [get_bd_intf_nets S00_AXIS_3_1] delete_bd_objs [get_bd_intf_nets S00_AXIS_4_1] delete_bd_objs [get_bd_intf_nets S00_AXIS_5_1] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0 endgroup set_property location {1 51 -400} [get_bd_cells Crossbar_Bypass_1x2_0] set_property location {1 -37 -503} [get_bd_cells Crossbar_Bypass_1x2_0] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] copy_bd_objs / [get_bd_cells {Crossbar_Bypass_1x2_0}] connect_bd_intf_net [get_bd_intf_ports S00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_ports S00_AXIS_1] [get_bd_intf_pins Crossbar_Bypass_1x2_1/S00_AXIS] connect_bd_intf_net [get_bd_intf_ports S00_AXIS_2] [get_bd_intf_pins Crossbar_Bypass_1x2_2/S00_AXIS] connect_bd_intf_net [get_bd_intf_ports S00_AXIS_3] [get_bd_intf_pins Crossbar_Bypass_1x2_3/S00_AXIS] connect_bd_intf_net [get_bd_intf_ports S00_AXIS_4] [get_bd_intf_pins Crossbar_Bypass_1x2_4/S00_AXIS] connect_bd_intf_net [get_bd_intf_ports S00_AXIS_5] [get_bd_intf_pins Crossbar_Bypass_1x2_5/S00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins AXIS_3x1_Muxes/S00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_0/M00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins AXIS_3x1_Muxes/S00_AXIS_1] [get_bd_intf_pins Crossbar_Bypass_1x2_1/M00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins AXIS_3x1_Muxes/S00_AXIS_2] [get_bd_intf_pins Crossbar_Bypass_1x2_2/M00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins AXIS_3x1_Muxes/S00_AXIS_3] [get_bd_intf_pins Crossbar_Bypass_1x2_3/M00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins AXIS_3x1_Muxes/S00_AXIS_4] [get_bd_intf_pins Crossbar_Bypass_1x2_4/M00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins AXIS_3x1_Muxes/S00_AXIS_5] [get_bd_intf_pins Crossbar_Bypass_1x2_5/M00_AXIS] group_bd_cells input_split [get_bd_cells Crossbar_Bypass_1x2_0] [get_bd_cells Crossbar_Bypass_1x2_1] [get_bd_cells Crossbar_Bypass_1x2_2] [get_bd_cells Crossbar_Bypass_1x2_3] [get_bd_cells Crossbar_Bypass_1x2_4] [get_bd_cells Crossbar_Bypass_1x2_5] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_6x1_Mux:1.0 AXIS_6x1_Mux_0 endgroup set_property location {4 852 -86} [get_bd_cells AXIS_6x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins input_split/Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins input_split/Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins input_split/Crossbar_Bypass_1x2_2/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins input_split/Crossbar_Bypass_1x2_3/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S03_AXIS] connect_bd_intf_net [get_bd_intf_pins input_split/Crossbar_Bypass_1x2_4/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S04_AXIS] connect_bd_intf_net [get_bd_intf_pins input_split/Crossbar_Bypass_1x2_5/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_0/S05_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_0/M00_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_A] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Fused_2x1Mux_Op:1.0 Fused_2x1Mux_Op_0 endgroup set_property location {1 -48 141} [get_bd_cells Fused_2x1Mux_Op_0] connect_bd_intf_net [get_bd_intf_pins Fused_2x1Mux_Op_0/M00_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_B] delete_bd_objs [get_bd_intf_nets Fused_2x1Mux_Op_0_M00_AXIS] startgroup create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0 endgroup set_property location {3 375 159} [get_bd_cells Crossbar_Bypass_1x2_0] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M00_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_B] connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Fused_2x1Mux_Op_0/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS] group_bd_cells Mux2x1_div [get_bd_cells Fused_2x1Mux_Op_0] [get_bd_cells Crossbar_Bypass_1x2_0] startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_1 endgroup set_property location {5 1893 21} [get_bd_cells floating_point_1] set_property -dict [list \ CONFIG.C_Latency {1} \ CONFIG.C_Mult_Usage {Full_Usage} \ CONFIG.C_Rate {1} \ CONFIG.C_Result_Exponent_Width {8} \ CONFIG.C_Result_Fraction_Width {24} \ CONFIG.Maximum_Latency {false} \ CONFIG.Operation_Type {Multiply} \ CONFIG.Result_Precision_Type {Single} \ ] [get_bd_cells floating_point_1] set_property location {5 1917 122} [get_bd_cells floating_point_1] startgroup create_bd_cell -type ip -vlnv ecelrc:user:AXIS_3x1_Mux:1.0 AXIS_3x1_Mux_0 endgroup set_property location {5 1864 -50} [get_bd_cells AXIS_3x1_Mux_0] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/VX_AXIS] [get_bd_intf_pins AXIS_3x1_Mux_0/S00_AXIS] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/VY_AXIS] [get_bd_intf_pins AXIS_3x1_Mux_0/S01_AXIS] connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/VZ_AXIS] [get_bd_intf_pins AXIS_3x1_Mux_0/S02_AXIS] connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Mux_0/M00_AXIS] [get_bd_intf_pins floating_point_1/S_AXIS_A] startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dt_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins floating_point_1/S_AXIS_B]] [get_bd_intf_ports dt_AXIS] connect_bd_intf_net [get_bd_intf_pins floating_point_1/S_AXIS_B] [get_bd_intf_ports dt_AXIS] endgroup connect_bd_intf_net [get_bd_intf_pins floating_point_1/M_AXIS_RESULT] [get_bd_intf_pins Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS] startgroup create_bd_port -dir I -type clk -freq_hz 100000000 clk connect_bd_net [get_bd_pins /floating_point_0/aclk] [get_bd_ports clk] endgroup connect_bd_net [get_bd_ports clk] [get_bd_pins Cascaded_FlipFlops_0/clk] connect_bd_net [get_bd_ports clk] [get_bd_pins floating_point_1/aclk] startgroup create_bd_port -dir I -from 1 -to 0 x_in connect_bd_net [get_bd_pins /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/select3x1] [get_bd_ports x_in] endgroup startgroup create_bd_port -dir I -from 1 -to 0 y_in connect_bd_net [get_bd_pins /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/select3x1] [get_bd_ports y_in] endgroup startgroup create_bd_port -dir I -from 1 -to 0 z_in connect_bd_net [get_bd_pins /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/select3x1] [get_bd_ports z_in] endgroup startgroup create_bd_port -dir I -from 1 -to 0 vx_in connect_bd_net [get_bd_pins /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/select3x1] [get_bd_ports vx_in] endgroup startgroup create_bd_port -dir I -from 1 -to 0 vy_in connect_bd_net [get_bd_pins /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/select3x1] [get_bd_ports vy_in] endgroup startgroup create_bd_port -dir I -from 1 -to 0 vz_in connect_bd_net [get_bd_pins /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/select3x1] [get_bd_ports vz_in] endgroup startgroup create_bd_port -dir I -from 2 -to 0 sum_sel connect_bd_net [get_bd_pins /AXIS_6x1_Mux_0/select6x1] [get_bd_ports sum_sel] endgroup startgroup create_bd_port -dir I op_select_divide connect_bd_net [get_bd_pins /Mux2x1_div/Fused_2x1Mux_Op_0/op_select] [get_bd_ports op_select_divide] endgroup startgroup create_bd_port -dir I div_sel connect_bd_net [get_bd_pins /Mux2x1_div/Fused_2x1Mux_Op_0/apply_op] [get_bd_ports div_sel] endgroup group_bd_cells Mux2x1_adder [get_bd_cells floating_point_0] [get_bd_cells AXIS_2x1_Mux_0] regenerate_bd_layout group_bd_cells Mux2x1_adder_out6 [get_bd_cells Mux2x1_adder] [get_bd_cells add_result] startgroup endgroup startgroup create_bd_port -dir I -from 1 -to 0 v_sel connect_bd_net [get_bd_pins /AXIS_3x1_Mux_0/select3x1] [get_bd_ports v_sel] endgroup startgroup create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 X_AXIS connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/X_AXIS] [get_bd_intf_ports X_AXIS] endgroup startgroup create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 Y_AXIS connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/Y_AXIS] [get_bd_intf_ports Y_AXIS] endgroup startgroup create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 Z_AXIS connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/Z_AXIS] [get_bd_intf_ports Z_AXIS] endgroup regenerate_bd_layout copy_bd_objs / [get_bd_cells {Mux2x1_adder_out6/add_result}] set_property location {2 506 750} [get_bd_cells add_result] set_property name constant_splitter [get_bd_cells add_result] startgroup create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 constant_AXIS set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS]] [get_bd_intf_ports constant_AXIS] connect_bd_intf_net [get_bd_intf_pins constant_splitter/S00_AXIS] [get_bd_intf_ports constant_AXIS] endgroup set_property location {5 1814 718} [get_bd_cells constant_splitter] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M01_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M01_AXIS1] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M01_AXIS2] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M00_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS] delete_bd_objs [get_bd_intf_nets constant_splitter_M00_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M01_AXIS3] [get_bd_intf_pins AXIS_3x1_Muxes/S02_AXIS3] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M00_AXIS] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS] connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter/M01_AXIS4] [get_bd_intf_pins AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS] regenerate_bd_layout set_property location {4 1353 752} [get_bd_cells constant_splitter] regenerate_bd_layout -routing regenerate_bd_layout save_bd_design Wrote : Wrote : make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -top CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /constant_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /Cascaded_FlipFlops_0/aresetn /Cascaded_FlipFlops_0/forward /Cascaded_FlipFlops_0/set_new /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/select2x1 Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v add_files -norecurse /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v update_compile_order -fileset sources_1 set_property top design_4_wrapper [current_fileset] update_compile_order -fileset sources_1 create_fileset -simset sim_5 file mkdir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new set_property SOURCE_SET sources_1 [get_filesets sim_5] close [ open /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v w ] add_files -fileset sim_5 /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v current_fileset -simset [ get_filesets sim_5 ] update_compile_order -fileset sim_5 set_property top tb_flow_test [get_filesets sim_5] set_property top_lib xil_defaultlib [get_filesets sim_5] update_compile_order -fileset sim_5 startgroup create_bd_port -dir I forward connect_bd_net [get_bd_pins /Cascaded_FlipFlops_0/forward] [get_bd_ports forward] endgroup startgroup create_bd_port -dir I -from 2 -to 0 set_new connect_bd_net [get_bd_pins /Cascaded_FlipFlops_0/set_new] [get_bd_ports set_new] endgroup startgroup create_bd_port -dir I -type rst aresetn connect_bd_net [get_bd_pins /Cascaded_FlipFlops_0/aresetn] [get_bd_ports aresetn] endgroup save_bd_design Wrote : Wrote : report_ip_status -name ip_status open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -top CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /constant_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/select2x1 Wrote : Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v ipx::edit_ip_in_project -upgrade true -name Fused_2x1Mux_Op_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Fused_2x1Mux_Op_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Fused_2x1Mux_Op_1_0/component.xml INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'. INFO: [IP_Flow 19-795] Syncing license key meta-data update_compile_order -fileset sources_1 set_property core_revision 3 [ipx::current_core] ipx::update_source_project_archive -component [ipx::current_core] ipx::create_xgui_files [ipx::current_core] ipx::update_checksums [ipx::current_core] ipx::check_integrity [ipx::current_core] WARNING: [IP_Flow 19-3158] Bus Interface 'S00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. WARNING: [IP_Flow 19-3158] Bus Interface 'M00_AXIS': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock. INFO: [IP_Flow 19-2181] Payment Required is not set for this core. INFO: [IP_Flow 19-2187] The Product Guide file is missing. INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed. ipx::save_core [ipx::current_core] ipx::move_temp_component_back -component [ipx::current_core] close_project -delete update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog. INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo' report_ip_status -name ip_status report_ip_status -name ip_status upgrade_ip -vlnv ecelrc:user:Fused_2x1Mux_Op:1.0 [get_ips design_4_Fused_2x1Mux_Op_0_0] -log ip_upgrade.log Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd' INFO: [IP_Flow 19-3422] Upgraded design_4_Fused_2x1Mux_Op_0_0 (Fused_2x1Mux_Op_v1.0 1.0) from revision 2 to revision 3 Wrote : Wrote : INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips design_4_Fused_2x1Mux_Op_0_0] -no_script -sync -force -quiet report_ip_status -name ip_status startgroup create_bd_port -dir I add_sel connect_bd_net [get_bd_pins /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/select2x1] [get_bd_ports add_sel] endgroup save_bd_design Wrote : Wrote : make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -top CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-968] AXI interface port /constant_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly. CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v close_sim INFO: [Simtcl 6-16] Simulation closed reset_run synth_1 INFO: [Project 1-1161] Replacing file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp with file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/synth_1/design_1_wrapper.dcp launch_runs synth_1 -jobs 36 INFO: [BD 41-1662] The design 'design_4.bd' is already validated. Therefore parameter propagation will not be re-run. Wrote : Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Muxes/AXIS_3x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Muxes/AXIS_3x1_Mux_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Muxes/AXIS_3x1_Mux_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Muxes/AXIS_3x1_Mux_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Muxes/AXIS_3x1_Mux_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Muxes/AXIS_3x1_Mux_5 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Cascaded_FlipFlops_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block input_split/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block input_split/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block input_split/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block input_split/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block input_split/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block input_split/Crossbar_Bypass_1x2_5 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_6x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_div/Fused_2x1Mux_Op_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_div/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block floating_point_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block AXIS_3x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/Mux2x1_adder/floating_point_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter/Crossbar_Bypass_1x2_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter/Crossbar_Bypass_1x2_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter/Crossbar_Bypass_1x2_2 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter/Crossbar_Bypass_1x2_3 . INFO: [BD 41-1029] Generation completed for the IP Integrator block constant_splitter/Crossbar_Bypass_1x2_4 . Exporting to file /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh Generated Hardware Definition File /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [IP_Flow 19-6930] IPCACHE: runCacheChecks() number of threads = 8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_2x1_Mux_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_2 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_3 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_4 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_5 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_3x1_Mux_0_6 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_AXIS_6x1_Mux_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Cascaded_FlipFlops_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_10 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_11 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_12 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_13 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_14 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_2 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_3 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_4 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_7 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_8 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_0_9 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_1_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_2_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_3_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Crossbar_Bypass_1x2_4_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_Fused_2x1Mux_Op_0_0 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_floating_point_0_1 INFO: [IP_Flow 19-6921] IPCACHE: Adding cache check func to thread queue for IP design_4_floating_point_1_0 INFO: [IP_Flow 19-8020] IPCACHE: runCacheChecks() calling threadPool finishWork() INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_2x1_Mux_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_8 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_7 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_10 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_9 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_11 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_1_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_12 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_2_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_4 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_13 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_3_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_5 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_14 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_4_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_3x1_Mux_0_6 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_2 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Fused_2x1Mux_Op_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_AXIS_6x1_Mux_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_3 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_floating_point_0_1 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_floating_point_1_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Cascaded_FlipFlops_0_0 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_4_Crossbar_Bypass_1x2_0_4 [Thu May 2 23:43:55 2024] Launched design_4_AXIS_3x1_Mux_0_3_synth_1, design_4_AXIS_3x1_Mux_0_5_synth_1, design_4_AXIS_3x1_Mux_0_2_synth_1, design_4_AXIS_3x1_Mux_0_4_synth_1, design_4_Cascaded_FlipFlops_0_0_synth_1, design_4_Crossbar_Bypass_1x2_4_1_synth_1, design_4_Crossbar_Bypass_1x2_0_4_synth_1, design_4_Crossbar_Bypass_1x2_0_0_synth_1, design_4_AXIS_3x1_Mux_0_1_synth_1, design_4_Crossbar_Bypass_1x2_0_1_synth_1, design_4_Crossbar_Bypass_1x2_3_1_synth_1, design_4_Crossbar_Bypass_1x2_0_2_synth_1, design_4_Crossbar_Bypass_1x2_0_3_synth_1, design_4_Crossbar_Bypass_1x2_2_1_synth_1, design_4_Crossbar_Bypass_1x2_1_1_synth_1, design_4_AXIS_3x1_Mux_0_0_synth_1, design_4_floating_point_1_0_synth_1, design_4_floating_point_0_1_synth_1, design_4_AXIS_2x1_Mux_0_0_synth_1, design_4_Fused_2x1Mux_Op_0_0_synth_1, design_4_AXIS_3x1_Mux_0_6_synth_1, design_4_Crossbar_Bypass_1x2_0_12_synth_1, design_4_Crossbar_Bypass_1x2_0_7_synth_1, design_4_Crossbar_Bypass_1x2_0_10_synth_1, design_4_Crossbar_Bypass_1x2_0_9_synth_1, design_4_Crossbar_Bypass_1x2_0_8_synth_1, design_4_Crossbar_Bypass_1x2_0_13_synth_1, design_4_Crossbar_Bypass_1x2_0_11_synth_1, design_4_Crossbar_Bypass_1x2_0_14_synth_1, design_4_AXIS_6x1_Mux_0_0_synth_1... Run output will be captured here: design_4_AXIS_3x1_Mux_0_3_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_3_synth_1/runme.log design_4_AXIS_3x1_Mux_0_5_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_5_synth_1/runme.log design_4_AXIS_3x1_Mux_0_2_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_2_synth_1/runme.log design_4_AXIS_3x1_Mux_0_4_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_4_synth_1/runme.log design_4_Cascaded_FlipFlops_0_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Cascaded_FlipFlops_0_0_synth_1/runme.log design_4_Crossbar_Bypass_1x2_4_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_4_1_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_4_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_4_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_0_synth_1/runme.log design_4_AXIS_3x1_Mux_0_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_1_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_1_synth_1/runme.log design_4_Crossbar_Bypass_1x2_3_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_3_1_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_2_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_2_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_3_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_3_synth_1/runme.log design_4_Crossbar_Bypass_1x2_2_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_2_1_synth_1/runme.log design_4_Crossbar_Bypass_1x2_1_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_1_1_synth_1/runme.log design_4_AXIS_3x1_Mux_0_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_0_synth_1/runme.log design_4_floating_point_1_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_floating_point_1_0_synth_1/runme.log design_4_floating_point_0_1_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_floating_point_0_1_synth_1/runme.log design_4_AXIS_2x1_Mux_0_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_2x1_Mux_0_0_synth_1/runme.log design_4_Fused_2x1Mux_Op_0_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Fused_2x1Mux_Op_0_0_synth_1/runme.log design_4_AXIS_3x1_Mux_0_6_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_3x1_Mux_0_6_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_12_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_12_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_7_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_7_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_10_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_10_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_9_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_9_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_8_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_8_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_13_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_13_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_11_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_11_synth_1/runme.log design_4_Crossbar_Bypass_1x2_0_14_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_Crossbar_Bypass_1x2_0_14_synth_1/runme.log design_4_AXIS_6x1_Mux_0_0_synth_1: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/design_4_AXIS_6x1_Mux_0_0_synth_1/runme.log [Thu May 2 23:43:58 2024] Launched synth_1... Run output will be captured here: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.runs/synth_1/runme.log launch_runs: Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 12616.676 ; gain = 0.000 ; free physical = 363717 ; free virtual = 375932 reset_run synth_1 reset_run design_4_AXIS_3x1_Mux_0_5_synth_1 reset_run design_4_AXIS_3x1_Mux_0_2_synth_1 reset_run design_4_AXIS_3x1_Mux_0_4_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_4_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_0_synth_1 reset_run design_4_AXIS_3x1_Mux_0_1_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_1_synth_1 reset_run design_4_Crossbar_Bypass_1x2_3_1_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_2_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_3_synth_1 reset_run design_4_Crossbar_Bypass_1x2_2_1_synth_1 reset_run design_4_Crossbar_Bypass_1x2_1_1_synth_1 reset_run design_4_AXIS_3x1_Mux_0_0_synth_1 reset_run design_4_AXIS_3x1_Mux_0_6_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_12_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_7_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_10_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_9_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_8_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_13_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_11_synth_1 reset_run design_4_Crossbar_Bypass_1x2_0_14_synth_1 reset_run design_4_AXIS_3x1_Mux_0_3_synth_1 reset_run design_4_Cascaded_FlipFlops_0_0_synth_1 reset_run design_4_Crossbar_Bypass_1x2_4_1_synth_1 reset_run design_4_floating_point_1_0_synth_1 reset_run design_4_floating_point_0_1_synth_1 reset_run design_4_AXIS_2x1_Mux_0_0_synth_1 reset_run design_4_Fused_2x1Mux_Op_0_0_synth_1 reset_run design_4_AXIS_6x1_Mux_0_0_synth_1 reset_simulation -simset sim_5 -mode behavioral set_property library xil_defaultlib [get_files] launch_simulation -simset [get_filesets sim_5 ] Command: launch_simulation -simset sim_5 INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test' INFO: [Vivado 12-12490] The selected simulation model for 'design_4_AXIS_2x1_Mux_0_0' IP changed to 'rtl' from '', the simulation run directory will be deleted. WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_5' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_5'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xvlog --incr --relax -prj tb_flow_test_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_flow_test INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl xvhdl --incr --relax -prj tb_flow_test_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling package unisim.vcomponents Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package mult_gen_v12_0_18.dsp_pkg Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_flow_test Compiling module xil_defaultlib.glbl Built simulation snapshot tb_flow_test_behav execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 13453.285 ; gain = 0.000 ; free physical = 364256 ; free virtual = 376485 INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_flow_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 13453.285 ; gain = 0.000 ; free physical = 364236 ; free virtual = 376461 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {AXIS_3x1_Mux_0_M00_AXIS}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {floating_point_1_M_AXIS_RESULT}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M00_AXIS}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M01_AXIS1}] true set_property SIM_ATTRIBUTE.MARK_SIM true [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M01_AXIS}] true close_sim INFO: [Simtcl 6-16] Simulation closed save_bd_design Wrote : Wrote : generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0 WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0 INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/synth/design_4_AXIS_3x1_Mux_0_5.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/synth/design_4_Cascaded_FlipFlops_0_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.vhdl'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.dcp'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v'. WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v'. INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties. export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet launch_simulation -simset [get_filesets sim_5 ] Command: launch_simulation -simset sim_5 INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_5' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_5'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xvlog --incr --relax -prj tb_flow_test_vlog.prj xvhdl --incr --relax -prj tb_flow_test_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_flow_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 13831.270 ; gain = 0.000 ; free physical = 364215 ; free virtual = 376440 open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_5 ] Command: launch_simulation -simset sim_5 INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_5' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_5'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xvlog --incr --relax -prj tb_flow_test_vlog.prj xvhdl --incr --relax -prj tb_flow_test_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_flow_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 13916.309 ; gain = 0.000 ; free physical = 364195 ; free virtual = 376421 current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/vx_new_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/vx_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_a_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_b_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_div/Fused_2x1Mux_Op_0/s00_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_div/Fused_2x1Mux_Op_0/m00_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/s00_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0}} WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-572] Protocol instance "/tb_flow_test/uut/design_4_i/AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" is non-functional for the following reason(s): Required port "ACLK" is missing current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_a_tvalid}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_a_tready}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_b_tvalid}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_b_tready}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tvalid}} current_wave_config {Untitled 9} Untitled 9 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tready}} restart INFO: [Wavedata 42-604] Simulation restarted run 200 ns open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd} startgroup endgroup close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation -simset [get_filesets sim_5 ] Command: launch_simulation -simset sim_5 INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test' WARNING: [Vivado 12-13277] Compiled library path does not exist: '' INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs INFO: [SIM-utils-51] Simulation object is 'sim_5' INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0' INFO: [USF-XSim-7] Finding pre-compiled libraries... INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_5'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xvlog --incr --relax -prj tb_flow_test_vlog.prj INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1 INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ INFO: [VRFC 10-311] analyzing module design_4 INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97 INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module design_4_wrapper INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module tb_flow_test xvhdl --incr --relax -prj tb_flow_test_vhdl.prj Waiting for jobs to finish... No pending jobs, compilation finished. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Vivado Simulator v2022.2 Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log Using 8 slave threads. Starting static elaboration Pass Through NonSizing Optimizer Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling package std.standard Compiling package std.textio Compiling package ieee.std_logic_1164 Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp Compiling package ieee.numeric_std Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts Compiling package ieee.math_real Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table... Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg Compiling package ieee.std_logic_arith Compiling package ieee.std_logic_signed Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg Compiling package floating_point_v7_1_15.flt_utils Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp Compiling package unisim.vcomponents Compiling package ieee.vital_timing Compiling package ieee.vital_primitives Compiling package unisim.vpkg Compiling package mult_gen_v12_0_18.dsp_pkg Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4 Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5 Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0 Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0 Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0 Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0 Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0 Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...] Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\] Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\] Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...] Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...] Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...] Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...] Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...] Compiling module unisims_ver.x_lut1_mux2 Compiling module unisims_ver.LUT1 Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_0_1 Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4 Compiling module xil_defaultlib.add_result_imp_1QSRQB1 Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0 Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0 Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1 Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...] Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...] Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...] Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...] Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...] Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...] Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...] Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...] Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...] Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...] Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...] Compiling module xil_defaultlib.design_4_floating_point_1_0 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9 Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1... Compiling module xil_defaultlib.input_split_imp_12MMC97 Compiling module xil_defaultlib.design_4 Compiling module xil_defaultlib.design_4_wrapper Compiling module xil_defaultlib.tb_flow_test Compiling module xil_defaultlib.glbl Built simulation snapshot tb_flow_test_behav execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 13916.309 ; gain = 0.000 ; free physical = 364152 ; free virtual = 376384 INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim' INFO: [USF-XSim-98] *** Running xsim with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4 INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS INFO: [Wavedata 42-564] Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s): There are no instances of module "design_3" in the design. WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s): Required port "ACLK" is missing INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time resolution is 1 ps source tb_flow_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:27 ; elapsed = 00:00:16 . Memory (MB): peak = 13916.309 ; gain = 0.000 ; free physical = 364151 ; free virtual = 376379 current_wave_config {Untitled 10} Untitled 10 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_a_tdata}} current_wave_config {Untitled 10} Untitled 10 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_b_tdata}} current_wave_config {Untitled 10} Untitled 10 add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} restart