#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Fri May  3 02:09:09 2024
# Process ID: 2758808
# Current directory: /misc/scratch/ahermez/Final_Project
# Command line: vivado
# Log file: /misc/scratch/ahermez/Final_Project/vivado.log
# Journal file: /misc/scratch/ahermez/Final_Project/vivado.jou
# Running On: kamek.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404276 MB
#-----------------------------------------------------------
start_gui
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
open_project /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue.
INFO: [Common 17-14] Message 'IP_Flow 19-3664' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
open_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 7471.961 ; gain = 322.594 ; free physical = 366324 ; free virtual = 378549
update_compile_order -fileset sources_1
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
Reading block design file </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd>...
Adding component instance block -- ecelrc:user:Cascaded_FlipFlops:1.0 - Cascaded_FlipFlops_0
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_0
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_1
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_2
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_3
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_4
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_5
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_5
Adding component instance block -- ecelrc:user:AXIS_6x1_Mux:1.0 - AXIS_6x1_Mux_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Fused_2x1Mux_Op:1.0 - Fused_2x1Mux_Op_0
Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_1
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_0
Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0
Adding component instance block -- ecelrc:user:AXIS_2x1_Mux:1.0 - AXIS_2x1_Mux_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4
Successfully read diagram <design_4> from block design file </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd>
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
INFO: [Vivado 12-5357] 'setup' step aborted
INFO: [Common 17-344] 'launch_simulation' was cancelled
set_property library xil_defaultlib [get_files]
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366208 ; free virtual = 378440
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366137 ; free virtual = 378364
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366132 ; free virtual = 378364
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:15 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366088 ; free virtual = 378315
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 2}
Untitled 2
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366110 ; free virtual = 378342
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366081 ; free virtual = 378309
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 3}
Untitled 3
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366085 ; free virtual = 378319
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 366074 ; free virtual = 378302
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
current_wave_config {Untitled 4}
Untitled 4
add_wave {{/tb_flow_test/x_in}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 365111 ; free virtual = 378286
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 365104 ; free virtual = 378274
current_wave_config {Untitled 5}
Untitled 5
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 5}
Untitled 5
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
current_wave_config {Untitled 5}
Untitled 5
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 5}
Untitled 5
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 365121 ; free virtual = 378298
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 365111 ; free virtual = 378283
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
ipx::edit_ip_in_project -upgrade true -name Cascaded_FlipFlops_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Cascaded_FlipFlops_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Cascaded_FlipFlops_1_0/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
update_compile_order -fileset sources_1
set_property core_revision 5 [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::check_integrity [ipx::current_core]
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
ipx::save_core [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo
WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog.
INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 364875 ; free virtual = 378052
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 364848 ; free virtual = 378021
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} 
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} 
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 364943 ; free virtual = 378121
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 364915 ; free virtual = 378089
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new_axis_tdata}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_new}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/inst/x_axis_tdata}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
ipx::edit_ip_in_project -upgrade true -name Cascaded_FlipFlops_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Cascaded_FlipFlops_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/Cascaded_FlipFlops_1_0/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
update_compile_order -fileset sources_1
launch_runs synth_1 -jobs 36
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Fri May  3 03:18:40 2024] Launched synth_1...
Run output will be captured here: /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/Cascaded_FlipFlops_v1_0_project/Cascaded_FlipFlops_v1_0_project.runs/synth_1/runme.log
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xczu7ev-ffvc1156-2-e
INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 363922 ; free virtual = 377106
INFO: [Netlist 29-17] Analyzing 198 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 363836 ; free virtual = 377020
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 198 instances were transformed.
  IBUF => IBUF (IBUFCTRL, INBUF): 198 instances

open_run: Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 9481.004 ; gain = 0.000 ; free physical = 363636 ; free virtual = 376842
set_property core_revision 6 [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::check_integrity [ipx::current_core]
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
ipx::save_core [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo
WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog.
INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 11157.305 ; gain = 0.000 ; free physical = 362803 ; free virtual = 376174
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 11157.305 ; gain = 0.000 ; free physical = 362790 ; free virtual = 376157
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 11165.309 ; gain = 0.000 ; free physical = 362795 ; free virtual = 376167
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 11165.309 ; gain = 0.000 ; free physical = 362770 ; free virtual = 376137
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:force_sm:1.0 force_sm_0
endgroup
set_property location {7.5 3326 147} [get_bd_cells force_sm_0]
delete_bd_objs [get_bd_intf_nets Cascaded_FlipFlops_0_X_AXIS] [get_bd_intf_ports X_AXIS]
delete_bd_objs [get_bd_intf_nets Cascaded_FlipFlops_0_Y_AXIS] [get_bd_intf_ports Y_AXIS]
delete_bd_objs [get_bd_intf_nets Cascaded_FlipFlops_0_Z_AXIS] [get_bd_intf_ports Z_AXIS]
connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/X_AXIS] [get_bd_intf_pins force_sm_0/x_axis]
connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/Y_AXIS] [get_bd_intf_pins force_sm_0/y_axis]
connect_bd_intf_net [get_bd_intf_pins Cascaded_FlipFlops_0/Z_AXIS] [get_bd_intf_pins force_sm_0/z_axis]
connect_bd_net [get_bd_ports clk] [get_bd_pins force_sm_0/aclk]
connect_bd_net [get_bd_ports aresetn] [get_bd_pins force_sm_0/aresetn]
startgroup
create_bd_port -dir I start_calculation
connect_bd_net [get_bd_pins /force_sm_0/start_calculation] [get_bd_ports start_calculation]
endgroup
create_peripheral ecelrc user reg_file_6x1 1.0 -dir /misc/scratch/ahermez/Final_Project/ip_repo
add_peripheral_interface S00_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface S01_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface S02_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface S03_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface S04_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface S05_AXIS -interface_mode slave -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface M00_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface M01_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface M02_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface M03_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface M04_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
add_peripheral_interface M05_AXIS -interface_mode master -axi_type stream [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
generate_peripheral [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
write_peripheral [ipx::find_open_core ecelrc:user:reg_file_6x1:1.0]
set_property  ip_repo_paths  {/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0 /misc/scratch/ahermez/Final_Project/ip_repo} [current_project]
update_ip_catalog -rebuild
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-3685] Ignored loading user repository '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0'. The path is contained within another repository.
WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog.
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
set_property  ip_repo_paths  /misc/scratch/ahermez/Final_Project/ip_repo [current_project]
update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
ipx::edit_ip_in_project -upgrade true -name reg_file_6x1_v1_0_project -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.tmp/reg_file_6x1_v1_0_project /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/component.xml
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
INFO: [IP_Flow 19-795] Syncing license key meta-data
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
ipx::merge_project_changes files [ipx::current_core]
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M00_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M01_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M02_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M03_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M04_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M05_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S00_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S01_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S02_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S03_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S04_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S05_AXIS.v'.
WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/component.xml' ignored by IP packager.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S04_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S05_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M04_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogsynthesis (Verilog Synthesis)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M05_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S04_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S05_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M00_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M01_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M02_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M03_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M04_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
WARNING: [IP_Flow 19-5109] File Group 'xilinx_verilogbehavioralsimulation (Verilog Simulation)': File '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M05_AXIS.v' does not exist in the project sources. It has been removed from the packaged IP. If still required, please add this file to the project, merge sources and re-package.
ipx::merge_project_changes hdl_parameters [ipx::current_core]
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M00_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M01_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M02_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M03_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M04_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M05_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S00_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S01_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S02_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S03_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S04_AXIS.v'.
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S05_AXIS.v'.
WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/component.xml' ignored by IP packager.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s00_axis_tlast s00_axis_tstrb) were removed from the interface 'S00_AXIS'. Please review the IP interface 'S00_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s01_axis_tlast s01_axis_tstrb) were removed from the interface 'S01_AXIS'. Please review the IP interface 'S01_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s02_axis_tlast s02_axis_tstrb) were removed from the interface 'S02_AXIS'. Please review the IP interface 'S02_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s03_axis_tlast s03_axis_tstrb) were removed from the interface 'S03_AXIS'. Please review the IP interface 'S03_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s04_axis_tlast s04_axis_tstrb) were removed from the interface 'S04_AXIS'. Please review the IP interface 'S04_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (s05_axis_tlast s05_axis_tstrb) were removed from the interface 'S05_AXIS'. Please review the IP interface 'S05_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m00_axis_tlast m00_axis_tstrb) were removed from the interface 'M00_AXIS'. Please review the IP interface 'M00_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m01_axis_tlast m01_axis_tstrb) were removed from the interface 'M01_AXIS'. Please review the IP interface 'M01_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m02_axis_tlast m02_axis_tstrb) were removed from the interface 'M02_AXIS'. Please review the IP interface 'M02_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m03_axis_tlast m03_axis_tstrb) were removed from the interface 'M03_AXIS'. Please review the IP interface 'M03_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m04_axis_tlast m04_axis_tstrb) were removed from the interface 'M04_AXIS'. Please review the IP interface 'M04_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4835] Multiple IP ports (m05_axis_tlast m05_axis_tstrb) were removed from the interface 'M05_AXIS'. Please review the IP interface 'M05_AXIS'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m04_axis_aresetn) was removed from the interface 'M04_AXIS_RST'. Please review the IP interface 'M04_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m04_axis_aclk) was removed from the interface 'M04_AXIS_CLK'. Please review the IP interface 'M04_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m02_axis_aresetn) was removed from the interface 'M02_AXIS_RST'. Please review the IP interface 'M02_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m02_axis_aclk) was removed from the interface 'M02_AXIS_CLK'. Please review the IP interface 'M02_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m01_axis_aresetn) was removed from the interface 'M01_AXIS_RST'. Please review the IP interface 'M01_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m01_axis_aclk) was removed from the interface 'M01_AXIS_CLK'. Please review the IP interface 'M01_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m03_axis_aresetn) was removed from the interface 'M03_AXIS_RST'. Please review the IP interface 'M03_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m03_axis_aclk) was removed from the interface 'M03_AXIS_CLK'. Please review the IP interface 'M03_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s04_axis_aresetn) was removed from the interface 'S04_AXIS_RST'. Please review the IP interface 'S04_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s04_axis_aclk) was removed from the interface 'S04_AXIS_CLK'. Please review the IP interface 'S04_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aresetn) was removed from the interface 'S00_AXIS_RST'. Please review the IP interface 'S00_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s00_axis_aclk) was removed from the interface 'S00_AXIS_CLK'. Please review the IP interface 'S00_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s03_axis_aresetn) was removed from the interface 'S03_AXIS_RST'. Please review the IP interface 'S03_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s03_axis_aclk) was removed from the interface 'S03_AXIS_CLK'. Please review the IP interface 'S03_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aresetn) was removed from the interface 'S02_AXIS_RST'. Please review the IP interface 'S02_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s02_axis_aclk) was removed from the interface 'S02_AXIS_CLK'. Please review the IP interface 'S02_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m05_axis_aresetn) was removed from the interface 'M05_AXIS_RST'. Please review the IP interface 'M05_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m05_axis_aclk) was removed from the interface 'M05_AXIS_CLK'. Please review the IP interface 'M05_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s05_axis_aresetn) was removed from the interface 'S05_AXIS_RST'. Please review the IP interface 'S05_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s05_axis_aclk) was removed from the interface 'S05_AXIS_CLK'. Please review the IP interface 'S05_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aresetn) was removed from the interface 'M00_AXIS_RST'. Please review the IP interface 'M00_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (m00_axis_aclk) was removed from the interface 'M00_AXIS_CLK'. Please review the IP interface 'M00_AXIS_CLK'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aresetn) was removed from the interface 'S01_AXIS_RST'. Please review the IP interface 'S01_AXIS_RST'.
CRITICAL WARNING: [IP_Flow 19-4834] IP port (s01_axis_aclk) was removed from the interface 'S01_AXIS_CLK'. Please review the IP interface 'S01_AXIS_CLK'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S00_AXIS'.
set_property is_enabled false [get_files  /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0.v]
set_property is_enabled true [get_files  /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0.v]
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M00_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M01_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M02_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M03_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M04_AXIS.v] -no_script -reset -force -quiet
remove_files  {/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M01_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M02_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M03_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M04_AXIS.v}
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M05_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S01_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S00_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S02_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S03_AXIS.v] -no_script -reset -force -quiet
remove_files  {/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_M05_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S01_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S00_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S02_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S03_AXIS.v}
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S04_AXIS.v] -no_script -reset -force -quiet
export_ip_user_files -of_objects  [get_files /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S05_AXIS.v] -no_script -reset -force -quiet
remove_files  {/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S04_AXIS.v /misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/hdl/reg_file_6x1_v1_0_S05_AXIS.v}
ipx::merge_project_changes files [ipx::current_core]
WARNING: [IP_Flow 19-5226] Project source file '/misc/scratch/ahermez/Final_Project/ip_repo/reg_file_6x1_1_0/component.xml' ignored by IP packager.
set_property core_revision 2 [ipx::current_core]
ipx::update_source_project_archive -component [ipx::current_core]
ipx::create_xgui_files [ipx::current_core]
ipx::update_checksums [ipx::current_core]
ipx::check_integrity [ipx::current_core]
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
ipx::save_core [ipx::current_core]
ipx::move_temp_component_back -component [ipx::current_core]
close_project -delete
update_ip_catalog -rebuild -repo_path /misc/scratch/ahermez/Final_Project/ip_repo
WARNING: [IP_Flow 19-395] Problem validating against XML schema: see 'xilinx:targetDRCs' : Unexpected empty element
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /misc/scratch/ahermez/Final_Project/ip_repo/force_state_machine_1_0/component.xml. This IP will not be included in the IP Catalog.
INFO: [IP_Flow 19-725] Reloaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'
set_property location {6.5 3167 168} [get_bd_cells force_sm_0]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0
endgroup
copy_bd_objs /  [get_bd_cells {floating_point_0}]
copy_bd_objs /  [get_bd_cells {floating_point_0}]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/A_INPUT_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_A]
startgroup
set_property -dict [list \
  CONFIG.C_Latency {1} \
  CONFIG.C_Mult_Usage {Full_Usage} \
  CONFIG.C_Rate {1} \
  CONFIG.C_Result_Exponent_Width {8} \
  CONFIG.C_Result_Fraction_Width {24} \
  CONFIG.Maximum_Latency {false} \
  CONFIG.Operation_Type {Multiply} \
  CONFIG.Result_Precision_Type {Single} \
] [get_bd_cells floating_point_0]
endgroup
set_property -dict [list \
  CONFIG.C_Latency {1} \
  CONFIG.C_Mult_Usage {Full_Usage} \
  CONFIG.C_Rate {1} \
  CONFIG.C_Result_Exponent_Width {8} \
  CONFIG.C_Result_Fraction_Width {24} \
  CONFIG.Maximum_Latency {false} \
  CONFIG.Operation_Type {Multiply} \
  CONFIG.Result_Precision_Type {Single} \
] [get_bd_cells floating_point_2]
set_property -dict [list \
  CONFIG.C_Latency {1} \
  CONFIG.Maximum_Latency {false} \
] [get_bd_cells floating_point_3]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/B_INPUT_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_B]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/C_INPUT_AXIS] [get_bd_intf_pins floating_point_2/S_AXIS_A]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/D_INPUT_AXIS] [get_bd_intf_pins floating_point_2/S_AXIS_B]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/E_INPUT_AXIS] [get_bd_intf_pins floating_point_3/S_AXIS_A]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/F_INPUT_AXIS] [get_bd_intf_pins floating_point_3/S_AXIS_B]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/OPERATION_AXIS] [get_bd_intf_pins floating_point_3/S_AXIS_OPERATION]
connect_bd_intf_net [get_bd_intf_pins floating_point_0/M_AXIS_RESULT] [get_bd_intf_pins force_sm_0/a_result_axis]
connect_bd_intf_net [get_bd_intf_pins floating_point_2/M_AXIS_RESULT] [get_bd_intf_pins force_sm_0/b_result_axis]
connect_bd_intf_net [get_bd_intf_pins floating_point_3/M_AXIS_RESULT] [get_bd_intf_pins force_sm_0/c_result_axis]
connect_bd_net [get_bd_ports clk] [get_bd_pins floating_point_0/aclk]
connect_bd_net [get_bd_ports clk] [get_bd_pins floating_point_2/aclk]
connect_bd_net [get_bd_ports clk] [get_bd_pins floating_point_3/aclk]
delete_bd_objs [get_bd_intf_nets S00_AXIS_8]
delete_bd_objs [get_bd_intf_ports constant_AXIS]
set_property location {4 1828 660} [get_bd_cells constant_splitter]
startgroup
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 const_axis
set_property CONFIG.TDATA_NUM_BYTES [get_property CONFIG.TDATA_NUM_BYTES [get_bd_intf_pins force_sm_0/const_axis]] [get_bd_intf_ports const_axis]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/const_axis] [get_bd_intf_ports const_axis]
endgroup
delete_bd_objs [get_bd_intf_nets AXIS_3x1_Mux_0_M00_AXIS]
set_property location {0.5 350 423} [get_bd_cells AXIS_3x1_Mux_0]
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:AXIS_2x1_Mux:1.0 AXIS_2x1_Mux_0
endgroup
set_property location {2.5 720 636} [get_bd_cells AXIS_2x1_Mux_0]
connect_bd_intf_net [get_bd_intf_pins AXIS_3x1_Mux_0/M00_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_0/S00_AXIS]
set_property location {8 3327 702} [get_bd_cells AXIS_2x1_Mux_0]
connect_bd_intf_net [get_bd_intf_pins force_sm_0/RESULT_AXIS] [get_bd_intf_pins AXIS_2x1_Mux_0/S01_AXIS]
startgroup
create_bd_port -dir I dt_select
connect_bd_net [get_bd_pins /AXIS_2x1_Mux_0/select2x1] [get_bd_ports dt_select]
endgroup
set_property location {2 942 626} [get_bd_cells AXIS_2x1_Mux_0]
connect_bd_intf_net [get_bd_intf_pins AXIS_2x1_Mux_0/M00_AXIS] [get_bd_intf_pins floating_point_1/S_AXIS_A]
group_bd_cells F_function [get_bd_cells floating_point_2] [get_bd_cells force_sm_0] [get_bd_cells floating_point_0] [get_bd_cells floating_point_3]
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:reg_file_6x1:1.0 reg_file_6x1_0
endgroup
set_property location {6 2532 874} [get_bd_cells reg_file_6x1_0]
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:AXIS_6x1_Mux:1.0 AXIS_6x1_Mux_1
endgroup
set_property location {7 2788 855} [get_bd_cells AXIS_6x1_Mux_1]
connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M00_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S00_AXIS]
connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M01_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S01_AXIS]
connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M02_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S02_AXIS]
connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M05_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S05_AXIS]
connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M04_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S04_AXIS]
connect_bd_intf_net [get_bd_intf_pins reg_file_6x1_0/M03_AXIS] [get_bd_intf_pins AXIS_6x1_Mux_1/S03_AXIS]
copy_bd_objs /  [get_bd_cells {constant_splitter}]
connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_1/M00_AXIS] -boundary_type upper [get_bd_intf_pins constant_splitter/S00_AXIS]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter1/M01_AXIS] [get_bd_intf_pins reg_file_6x1_0/S00_AXIS]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter1/M01_AXIS1] [get_bd_intf_pins reg_file_6x1_0/S01_AXIS]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter1/M01_AXIS2] [get_bd_intf_pins reg_file_6x1_0/S02_AXIS]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter1/M01_AXIS3] [get_bd_intf_pins reg_file_6x1_0/S03_AXIS]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter1/M00_AXIS] [get_bd_intf_pins reg_file_6x1_0/S04_AXIS]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins constant_splitter1/M01_AXIS4] [get_bd_intf_pins reg_file_6x1_0/S05_AXIS]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0
endgroup
set_property -dict [list \
  CONFIG.Add_Sub_Value {Add} \
  CONFIG.C_Latency {1} \
  CONFIG.Maximum_Latency {false} \
] [get_bd_cells floating_point_0]
connect_bd_intf_net [get_bd_intf_pins floating_point_0/M_AXIS_RESULT] -boundary_type upper [get_bd_intf_pins constant_splitter1/S00_AXIS]
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:Fused_2x1Mux_Op:1.0 Fused_2x1Mux_Op_0
endgroup
delete_bd_objs [get_bd_intf_nets AXIS_6x1_Mux_1_M00_AXIS]
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_0
endgroup
connect_bd_intf_net [get_bd_intf_pins AXIS_6x1_Mux_1/M00_AXIS] [get_bd_intf_pins Crossbar_Bypass_1x2_0/S00_AXIS]
connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M00_AXIS] -boundary_type upper [get_bd_intf_pins constant_splitter/S00_AXIS]
connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_0/M01_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_A]
connect_bd_intf_net [get_bd_intf_pins Fused_2x1Mux_Op_0/M00_AXIS] [get_bd_intf_pins floating_point_0/S_AXIS_B]
delete_bd_objs [get_bd_intf_nets floating_point_1_M_AXIS_RESULT]
startgroup
create_bd_cell -type ip -vlnv ecelrc:user:Crossbar_Bypass_1x2:1.0 Crossbar_Bypass_1x2_1
endgroup
connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M00_AXIS] -boundary_type upper [get_bd_intf_pins Mux2x1_div/S00_AXIS]
connect_bd_intf_net [get_bd_intf_pins Crossbar_Bypass_1x2_1/M01_AXIS] [get_bd_intf_pins Fused_2x1Mux_Op_0/S00_AXIS]
connect_bd_intf_net [get_bd_intf_pins floating_point_1/M_AXIS_RESULT] [get_bd_intf_pins Crossbar_Bypass_1x2_1/S00_AXIS]
startgroup
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/clk (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}}  [get_bd_pins floating_point_0/aclk]
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/clk (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}}  [get_bd_pins reg_file_6x1_0/clk]
endgroup
startgroup
create_bd_port -dir I -from 2 -to 0 acc_select
connect_bd_net [get_bd_pins /AXIS_6x1_Mux_1/select6x1] [get_bd_ports acc_select]
endgroup
startgroup
create_bd_port -dir I mul_select
connect_bd_net [get_bd_pins /Fused_2x1Mux_Op_0/apply_op] [get_bd_ports mul_select]
endgroup
startgroup
create_bd_port -dir I op_select_mult
connect_bd_net [get_bd_pins /Fused_2x1Mux_Op_0/op_select] [get_bd_ports op_select_mult]
endgroup
startgroup
create_bd_port -dir I -from 2 -to 0 acc_ld_ctr
connect_bd_net [get_bd_pins /reg_file_6x1_0/ld_ctr] [get_bd_ports acc_ld_ctr]
endgroup
regenerate_bd_layout
group_bd_cells dt_multiplier [get_bd_cells floating_point_1] [get_bd_cells Crossbar_Bypass_1x2_1]
group_bd_cells acc_mux [get_bd_cells AXIS_6x1_Mux_1] [get_bd_cells Crossbar_Bypass_1x2_0]
regenerate_bd_layout
save_bd_design
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd> 
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ui/bd_20d81e53.ui> 
make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -top
ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'design_4.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
design_4_Cascaded_FlipFlops_0_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
report_ip_status -name ip_status 
upgrade_ip [get_ips  {design_2_Cascaded_FlipFlops_0_0 design_4_Cascaded_FlipFlops_0_0}] -log ip_upgrade.log
Reading block design file </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd>...
Adding component instance block -- ecelrc:user:Cascaded_FlipFlops:1.0 - Cascaded_FlipFlops_0
Successfully read diagram <design_2> from block design file </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd>
Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd'
INFO: [IP_Flow 19-3422] Upgraded design_2_Cascaded_FlipFlops_0_0 (Cascaded_FlipFlops_v1.0 1.0) from revision 4 to revision 6
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_2/design_2.bd> 
Upgrading '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd'
INFO: [IP_Flow 19-3422] Upgraded design_4_Cascaded_FlipFlops_0_0 (Cascaded_FlipFlops_v1.0 1.0) from revision 4 to revision 6
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd> 
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ui/bd_20d81e53.ui> 
INFO: [Coretcl 2-1525] Wrote upgrade log to '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/ip_upgrade.log'.
export_ip_user_files -of_objects [get_ips {design_2_Cascaded_FlipFlops_0_0 design_4_Cascaded_FlipFlops_0_0}] -no_script -sync -force -quiet
report_ip_status -name ip_status 
make_wrapper -files [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -top
CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.
CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_1 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.
CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_2 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.
CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_3 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.
CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_4 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.
CRITICAL WARNING: [BD 41-968] AXI interface port /S00_AXIS_5 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S03_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S04_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/S05_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_6x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /input_split/Crossbar_Bypass_1x2_5/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_1/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_2/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_3/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter/Crossbar_Bypass_1x2_4/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/S00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M00_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_0/M01_AXIS is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-967] AXI interface pin /constant_splitter1/Crossbar_Bypass_1x2_1/S00_AXIS is not associated to any clock pin. It may not work correctly.
INFO: [Common 17-14] Message 'BD 41-967' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd> 
Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v
Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v
Verilog Output written to : /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v
create_fileset -simset sim_6
file mkdir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new
set_property SOURCE_SET sources_1 [get_filesets sim_6]
close [ open /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v w ]
add_files -fileset sim_6 /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_6/new/tb_main_system.v
current_fileset -simset [ get_filesets sim_6 ]
update_compile_order -fileset sim_6
set_property top tb_main_system [get_filesets sim_6]
set_property top_lib xil_defaultlib [get_filesets sim_6]
update_compile_order -fileset sim_6
close_sim