#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Fri May  3 00:11:14 2024
# Process ID: 3831213
# Current directory: /misc/scratch/ahermez/Final_Project
# Command line: vivado
# Log file: /misc/scratch/ahermez/Final_Project/vivado.log
# Journal file: /misc/scratch/ahermez/Final_Project/vivado.jou
# Running On: kamek.ece.utexas.edu, OS: Linux, CPU Frequency: 3900.000 MHz, CPU Physical cores: 32, Host memory: 404276 MB
#-----------------------------------------------------------
start_gui
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
open_project /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/misc/scratch/ahermez/Final_Project/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Cascaded_FlipFlops_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_2' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_3' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_4' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_5' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_7' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_8' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_9' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_10' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_11' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_12' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_6x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Crossbar_Bypass_1x2_0_13' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_Fused_2x1Mux_Op_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_1_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_3x1_Mux_0_6' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_floating_point_0_1' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_4_AXIS_2x1_Mux_0_0' generated file not found '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0_sim_netlist.vhdl'. Please regenerate to continue.
INFO: [Common 17-14] Message 'IP_Flow 19-3664' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
open_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 7480.062 ; gain = 333.941 ; free physical = 366037 ; free virtual = 378265
update_compile_order -fileset sources_1
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
Reading block design file </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd>...
Adding component instance block -- ecelrc:user:Cascaded_FlipFlops:1.0 - Cascaded_FlipFlops_0
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_0
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_1
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_2
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_3
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_4
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_5
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_5
Adding component instance block -- ecelrc:user:AXIS_6x1_Mux:1.0 - AXIS_6x1_Mux_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Fused_2x1Mux_Op:1.0 - Fused_2x1Mux_Op_0
Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_1
Adding component instance block -- ecelrc:user:AXIS_3x1_Mux:1.0 - AXIS_3x1_Mux_0
Adding component instance block -- xilinx.com:ip:floating_point:7.1 - floating_point_0
Adding component instance block -- ecelrc:user:AXIS_2x1_Mux:1.0 - AXIS_2x1_Mux_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_0
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_1
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_2
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_3
Adding component instance block -- ecelrc:user:Crossbar_Bypass_1x2:1.0 - Crossbar_Bypass_1x2_4
Successfully read diagram <design_4> from block design file </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd>
set_property library xil_defaultlib [get_files]
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 9422.676 ; gain = 0.000 ; free physical = 365869 ; free virtual = 378098
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_a_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/s_axis_b_tdata}} 
current_wave_config {Untitled 1}
Untitled 1
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M01_AXIS}]
set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M00_AXIS}]
set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {Crossbar_Bypass_1x2_0_M01_AXIS1}]
set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {floating_point_1_M_AXIS_RESULT}]
set_property SIM_ATTRIBUTE.MARK_SIM {} [get_bd_intf_nets {AXIS_3x1_Mux_0_M00_AXIS}]
save_bd_design
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd> 
Wrote  : </misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ui/bd_20d81e53.ui> 
close_sim
INFO: [Simtcl 6-16] Simulation closed
generate_target Simulation [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd]
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Muxes/AXIS_3x1_Mux_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS_5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS1 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS2 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS3 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS4 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS5 could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_1
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_2
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_3
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_4
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /input_split/Crossbar_Bypass_1x2_5
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S02_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S03_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S04_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S05_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_6x1_Mux_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M01_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Crossbar_Bypass_1x2_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin M00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /Mux2x1_div/Fused_2x1Mux_Op_0
WARNING: [BD 41-2265] Clock pin for protocol instance pin S00_AXIS could not be determined. Make sure that ASSOCIATED_BUSIF and ASSOCIATED_RESET properties are set or propagated on clock pins of block /AXIS_3x1_Mux_0
INFO: [Common 17-14] Message 'BD 41-2265' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/design_4_Crossbar_Bypass_1x2_0_8.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/design_4_Crossbar_Bypass_1x2_0_9.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/design_4_Crossbar_Bypass_1x2_0_10.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/design_4_Crossbar_Bypass_1x2_0_11.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/design_4_Crossbar_Bypass_1x2_0_12.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/design_4_AXIS_6x1_Mux_0_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/design_4_Fused_2x1Mux_Op_0_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/design_4_Crossbar_Bypass_1x2_0_13.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_1_0/design_4_floating_point_1_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/design_4_AXIS_3x1_Mux_0_6.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_floating_point_0_1/design_4_floating_point_0_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/design_4_AXIS_2x1_Mux_0_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/design_4_Crossbar_Bypass_1x2_0_0.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/design_4_Crossbar_Bypass_1x2_0_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/design_4_Crossbar_Bypass_1x2_0_2.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/design_4_Crossbar_Bypass_1x2_0_3.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/design_4_Crossbar_Bypass_1x2_0_4.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/design_4_Crossbar_Bypass_1x2_0_14.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/design_4_Crossbar_Bypass_1x2_1_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/design_4_Crossbar_Bypass_1x2_2_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/design_4_Crossbar_Bypass_1x2_3_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/design_4_Crossbar_Bypass_1x2_4_1.xci'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4_ooc.xdc'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hw_handoff/design_4.hwh'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/design_4.bda'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/synth/design_4.hwdef'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/sim/design_4.protoinst'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/design_4_AXIS_3x1_Mux_0_0.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/synth/design_4_AXIS_3x1_Mux_0_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/design_4_AXIS_3x1_Mux_0_1.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/synth/design_4_AXIS_3x1_Mux_0_1.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/design_4_AXIS_3x1_Mux_0_2.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/synth/design_4_AXIS_3x1_Mux_0_2.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/design_4_AXIS_3x1_Mux_0_3.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/synth/design_4_AXIS_3x1_Mux_0_3.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/design_4_AXIS_3x1_Mux_0_4.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/synth/design_4_AXIS_3x1_Mux_0_4.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/design_4_AXIS_3x1_Mux_0_5.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/synth/design_4_AXIS_3x1_Mux_0_5.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/design_4_Cascaded_FlipFlops_0_0.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/synth/design_4_Cascaded_FlipFlops_0_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_sim_netlist.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.vhdl'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7_stub.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/design_4_Crossbar_Bypass_1x2_0_7.dcp'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v'.
WARNING: [Vivado 12-4154] User modified property 'Library' (with value 'xil_defaultlib') was detected on '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v'.
INFO: [Common 17-14] Message 'Vivado 12-4154' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Vivado 12-4152] One or more user modified properties were detected. The reset_target command can be used to reset the targets data which will also reset all target properties.
export_ip_user_files -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -no_script -sync -force -quiet
export_simulation -of_objects [get_files /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd] -directory /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/sim_scripts -ip_user_files_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files -ipstatic_source_dir /misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/ipstatic -lib_map_path [list {modelsim=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/modelsim} {questa=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/questa} {xcelium=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/xcelium} {vcs=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/vcs} {riviera=/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365810 ; free virtual = 378039
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365836 ; free virtual = 378070
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365815 ; free virtual = 378045
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365430 ; free virtual = 377632
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365210 ; free virtual = 377438
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365739 ; free virtual = 377978
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365721 ; free virtual = 377955
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:19 ; elapsed = 00:00:10 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365251 ; free virtual = 377475
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:26 ; elapsed = 00:00:17 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365121 ; free virtual = 377353
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 6}
Untitled 6
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365676 ; free virtual = 377917
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:23 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365660 ; free virtual = 377897
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 7}
Untitled 7
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
open_bd_design {/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sources_1/bd/design_4/design_4.bd}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365599 ; free virtual = 377842
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365575 ; free virtual = 377814
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 8}
Untitled 8
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365585 ; free virtual = 377830
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365574 ; free virtual = 377814
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365580 ; free virtual = 377824
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365573 ; free virtual = 377813
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/vx_new_axis_tdata}} 
current_wave_config {Untitled 10}
Untitled 10
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/vx_axis_tdata}} 
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365491 ; free virtual = 377736
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365472 ; free virtual = 377712
current_wave_config {Untitled 11}
Untitled 11
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_new_axis_tdata}} 
current_wave_config {Untitled 11}
Untitled 11
add_wave {{/tb_flow_test/uut/design_4_i/Cascaded_FlipFlops_0/x_axis_tdata}} 
current_wave_config {Untitled 11}
Untitled 11
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 11}
Untitled 11
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365567 ; free virtual = 377812
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365549 ; free virtual = 377790
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365574 ; free virtual = 377820
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365562 ; free virtual = 377804
current_wave_config {Untitled 13}
Untitled 13
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 13}
Untitled 13
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 13}
Untitled 13
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 13}
Untitled 13
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365575 ; free virtual = 377821
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365545 ; free virtual = 377786
current_wave_config {Untitled 14}
Untitled 14
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 14}
Untitled 14
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 14}
Untitled 14
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 14}
Untitled 14
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365552 ; free virtual = 377799
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:15 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365524 ; free virtual = 377766
current_wave_config {Untitled 15}
Untitled 15
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 15}
Untitled 15
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 15}
Untitled 15
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 15}
Untitled 15
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365519 ; free virtual = 377765
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365507 ; free virtual = 377749
current_wave_config {Untitled 16}
Untitled 16
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 16}
Untitled 16
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 16}
Untitled 16
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 16}
Untitled 16
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365693 ; free virtual = 377922
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:30 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365678 ; free virtual = 377904
current_wave_config {Untitled 17}
Untitled 17
add_wave {{/tb_flow_test/uut/design_4_i/floating_point_1/m_axis_result_tdata}} 
current_wave_config {Untitled 17}
Untitled 17
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_a_tdata}} 
current_wave_config {Untitled 17}
Untitled 17
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/s_axis_b_tdata}} 
current_wave_config {Untitled 17}
Untitled 17
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/m_axis_result_tdata}} 
current_wave_config {Untitled 17}
Untitled 17
add_wave {{/tb_flow_test/uut/design_4_i/Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/m00_axis_tdata}} 
restart
INFO: [Wavedata 42-604] Simulation restarted
run 200 ns
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365667 ; free virtual = 377898
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365628 ; free virtual = 377855
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation -simset [get_filesets sim_5 ]
Command: launch_simulation  -simset sim_5
INFO: [Vivado 12-12493] Simulation top is 'tb_flow_test'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_5'
INFO: [SIM-utils-72] Using boost library from '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_flow_test' in fileset 'sim_5'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_5'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xvlog --incr --relax -prj tb_flow_test_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/0094/hdl/Cascaded_FlipFlops_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Cascaded_FlipFlops_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Cascaded_FlipFlops_0_0/sim/design_4_Cascaded_FlipFlops_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Cascaded_FlipFlops_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/10fc/hdl/AXIS_3x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_0/sim/design_4_AXIS_3x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_1/sim/design_4_AXIS_3x1_Mux_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_2/sim/design_4_AXIS_3x1_Mux_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_3/sim/design_4_AXIS_3x1_Mux_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_4/sim/design_4_AXIS_3x1_Mux_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_5/sim/design_4_AXIS_3x1_Mux_0_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_5
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/715d/hdl/Crossbar_Bypass_1x2_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Crossbar_Bypass_1x2_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_7/sim/design_4_Crossbar_Bypass_1x2_0_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_7
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_8/sim/design_4_Crossbar_Bypass_1x2_0_8.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_8
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_9/sim/design_4_Crossbar_Bypass_1x2_0_9.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_9
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_10/sim/design_4_Crossbar_Bypass_1x2_0_10.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_10
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_11/sim/design_4_Crossbar_Bypass_1x2_0_11.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_11
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_12/sim/design_4_Crossbar_Bypass_1x2_0_12.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_12
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/1f39/hdl/AXIS_6x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_6x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_6x1_Mux_0_0/sim/design_4_AXIS_6x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_6x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_13/sim/design_4_Crossbar_Bypass_1x2_0_13.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_13
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/e08a/hdl/Fused_2x1Mux_Op_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Fused_2x1Mux_Op_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Fused_2x1Mux_Op_0_0/sim/design_4_Fused_2x1Mux_Op_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Fused_2x1Mux_Op_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_1_0/sim/design_4_floating_point_1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_3x1_Mux_0_6/sim/design_4_AXIS_3x1_Mux_0_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_3x1_Mux_0_6
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_floating_point_0_1/sim/design_4_floating_point_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_floating_point_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ipshared/8f99/hdl/AXIS_2x1_Mux_v1_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_2x1_Mux_v1_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_AXIS_2x1_Mux_0_0/sim/design_4_AXIS_2x1_Mux_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_AXIS_2x1_Mux_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_0/sim/design_4_Crossbar_Bypass_1x2_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_1/sim/design_4_Crossbar_Bypass_1x2_0_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_2/sim/design_4_Crossbar_Bypass_1x2_0_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_2
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_3/sim/design_4_Crossbar_Bypass_1x2_0_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_3
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_4/sim/design_4_Crossbar_Bypass_1x2_0_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_4
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_0_14/sim/design_4_Crossbar_Bypass_1x2_0_14.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_0_14
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_1_1/sim/design_4_Crossbar_Bypass_1x2_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_1_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_2_1/sim/design_4_Crossbar_Bypass_1x2_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_2_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_3_1/sim/design_4_Crossbar_Bypass_1x2_3_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_3_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/ip/design_4_Crossbar_Bypass_1x2_4_1/sim/design_4_Crossbar_Bypass_1x2_4_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_Crossbar_Bypass_1x2_4_1
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.ip_user_files/bd/design_4/sim/design_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AXIS_3x1_Muxes_imp_I9XJ4B
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_imp_18URLDB
INFO: [VRFC 10-311] analyzing module Mux2x1_adder_out6_imp_1Y08VR
INFO: [VRFC 10-311] analyzing module Mux2x1_div_imp_1HQ1UPU
INFO: [VRFC 10-311] analyzing module add_result_imp_1QSRQB1
INFO: [VRFC 10-311] analyzing module constant_splitter_imp_RFARGJ
INFO: [VRFC 10-311] analyzing module design_4
INFO: [VRFC 10-311] analyzing module input_split_imp_12MMC97
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.gen/sources_1/bd/design_4/hdl/design_4_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_4_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.srcs/sim_5/new/tb_flow_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_flow_test
xvhdl --incr --relax -prj tb_flow_test_vhdl.prj
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L floating_point_v7_1_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_flow_test_behav xil_defaultlib.tb_flow_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_viv_comp
Compiling package ieee.numeric_std
Compiling package xbip_utils_v3_0_10.xbip_utils_v3_0_10_pkg
Compiling package axi_utils_v2_0_6.axi_utils_v2_0_6_pkg
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_exp_table...
Compiling package mult_gen_v12_0_18.mult_gen_v12_0_18_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_15.floating_point_v7_1_15_pkg
Compiling package floating_point_v7_1_15.flt_utils
Compiling package xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv_comp
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package mult_gen_v12_0_18.dsp_pkg
Compiling module xil_defaultlib.AXIS_3x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_6
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_0
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_1
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_2
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_3
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_4
Compiling module xil_defaultlib.design_4_AXIS_3x1_Mux_0_5
Compiling module xil_defaultlib.AXIS_3x1_Muxes_imp_I9XJ4B
Compiling module xil_defaultlib.AXIS_6x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_6x1_Mux_0_0
Compiling module xil_defaultlib.Cascaded_FlipFlops_v1_0
Compiling module xil_defaultlib.design_4_Cascaded_FlipFlops_0_0
Compiling module xil_defaultlib.AXIS_2x1_Mux_v1_0
Compiling module xil_defaultlib.design_4_AXIS_2x1_Mux_0_0
Compiling architecture xilinx of entity axi_utils_v2_0_6.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=24,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(c_part="xczu7ev...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=5,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=0,adreg=0,alum...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_15.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=10,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=4,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(length=0,fast_input=true)...]
Compiling architecture rtl of entity floating_point_v7_1_15.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_15.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_15.compare [\compare(c_xdevicefamily="zynqup...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=23,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_add [\flt_add(c_xdevicefamily="zynqup...]
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_0_1
Compiling module xil_defaultlib.Mux2x1_adder_imp_18URLDB
Compiling module xil_defaultlib.Crossbar_Bypass_1x2_v1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_2
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_3
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_4
Compiling module xil_defaultlib.add_result_imp_1QSRQB1
Compiling module xil_defaultlib.Mux2x1_adder_out6_imp_1Y08VR
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.Fused_2x1Mux_Op_v1_0
Compiling module xil_defaultlib.design_4_Fused_2x1Mux_Op_0_0
Compiling module xil_defaultlib.Mux2x1_div_imp_1HQ1UPU
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_1_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_2_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_3_1
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_4_1
Compiling module xil_defaultlib.constant_splitter_imp_RFARGJ
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=26,length=0,fast_in...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,alumodereg=0...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.delay_line [\delay_line(c_xdevicefamily="zyn...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.op_resize [\op_resize(ai_width=24,bi_width=...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.dsp [\dsp(c_xdevicefamily="zynquplus"...]
Compiling architecture xilinx of entity mult_gen_v12_0_18.mult_gen_v12_0_18_viv [\mult_gen_v12_0_18_viv(c_verbosi...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult_xx [\fix_mult_xx(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.fix_mult [\fix_mult(c_xdevicefamily="zynqu...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=8,length=0,fast_inp...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=3,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=14,length=0)\]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_exp [\flt_mult_exp(c_xdevicefamily="z...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=12,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_6.xbip_pipe_v3_0_6_viv [\xbip_pipe_v3_0_6_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_15.delay [\delay(width=25,length=0,fast_in...]
Compiling architecture struct of entity floating_point_v7_1_15.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_round_bit [\flt_round_bit(c_xdevicefamily="...]
Compiling architecture rtl of entity floating_point_v7_1_15.renorm_and_round_logic [\renorm_and_round_logic(c_xdevic...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult_round [\flt_mult_round(c_xdevicefamily=...]
Compiling architecture synth of entity floating_point_v7_1_15.flt_dec_op_lat [\flt_dec_op_lat(c_xdevicefamily=...]
Compiling architecture rtl of entity floating_point_v7_1_15.flt_mult [\flt_mult(c_xdevicefamily="zynqu...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15_viv [\floating_point_v7_1_15_viv(c_xd...]
Compiling architecture xilinx of entity floating_point_v7_1_15.floating_point_v7_1_15 [\floating_point_v7_1_15(c_xdevic...]
Compiling module xil_defaultlib.design_4_floating_point_1_0
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_7
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_8
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_9
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.design_4_Crossbar_Bypass_1x2_0_1...
Compiling module xil_defaultlib.input_split_imp_12MMC97
Compiling module xil_defaultlib.design_4
Compiling module xil_defaultlib.design_4_wrapper
Compiling module xil_defaultlib.tb_flow_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_flow_test_behav
execute_script: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365609 ; free virtual = 377840
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/misc/scratch/ahermez/Final_Project/FP_Unit_Test/FP_Unit_Test.sim/sim_5/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_flow_test_behav -key {Behavioral:sim_5:Functional:tb_flow_test} -tclbatch {tb_flow_test.tcl} -protoinst "protoinst_files/design_4.protoinst" -protoinst "protoinst_files/design_3.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_4.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VX_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VY_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/VZ_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/X_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Y_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/Z_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vx_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vy_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/vz_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/x_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/y_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Cascaded_FlipFlops_0/z_new_axis
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/M_AXIS_RESULT
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/floating_point_0/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_A
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S_AXIS_B
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS
INFO: [Wavedata 42-564]   Found protocol instance at /tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS
INFO: [Common 17-14] Message 'Wavedata 42-564' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_3.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/design_3.protoinst for the following reason(s):
There are no instances of module "design_3" in the design.

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_1/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_2/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_3/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_4/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/AXIS_3x1_Mux_5/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/M00_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S00_AXIS_5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S01_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_3x1_Muxes/S02_AXIS5" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S02_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S03_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S04_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//AXIS_6x1_Mux_0/S05_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/AXIS_2x1_Mux_0/S01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/Mux2x1_adder/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_1/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_2/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_3/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/Crossbar_Bypass_1x2_4/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS1" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS2" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS3" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/M01_AXIS4" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_adder_out6/add_result/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Crossbar_Bypass_1x2_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/Fused_2x1Mux_Op_0/S00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M00_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

WARNING: [Wavedata 42-559] Protocol instance "/tb_flow_test/uut/design_4_i//Mux2x1_div/M01_AXIS" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

INFO: [Common 17-14] Message 'Wavedata 42-559' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Time resolution is 1 ps
source tb_flow_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_flow_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:31 ; elapsed = 00:00:16 . Memory (MB): peak = 9729.660 ; gain = 0.000 ; free physical = 365598 ; free virtual = 377825
restart