#-----------------------------------------------------------
# Vivado v2022.2 (64-bit)
# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
# Start of session at: Mon Feb 26 15:19:36 2024
# Process ID: 2308561
# Current directory: /home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2
# Command line: vivado ultra96v2_oob.xpr
# Log file: /home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2/vivado.log
# Journal file: /home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2/vivado.jou
# Running On: bowser.ece.utexas.edu, OS: Linux, CPU Frequency: 3546.733 MHz, CPU Physical cores: 32, Host memory: 404275 MB
#-----------------------------------------------------------
start_gui
open_project ultra96v2_oob.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:au280_es1:part0:1.0 available at /home/ecelrc/faculty/mcdermot/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/au280/es1/1.0/1.0/board.xml as part xcu280-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:au280_es1:part0:1.1 available at /home/ecelrc/faculty/mcdermot/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/au280/es1/1.1/1.1/board.xml as part xcu280-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.0 available at /home/ecelrc/faculty/mcdermot/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.0/1.0/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128_es:part0:1.1 available at /home/ecelrc/faculty/mcdermot/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu128/es/1.1/1.1/board.xml as part xcvu37p-fsvh2892-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129_es:part0:1.0 available at /home/ecelrc/faculty/mcdermot/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/vcu129/es/1.0/1.0/board.xml as part xcvu29p-fsga2577-2l-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at /home/ecelrc/faculty/mcdermot/.Xilinx/Vivado/2019.2/xhub/board_store/XilinxBoardStore/Vivado/2019.2/boards/Xilinx/zcu216/1.0/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/packages/Xilinx_2022.2/Vivado/2022.2/data/ip'.
open_project: Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 7672.016 ; gain = 575.891 ; free physical = 200761 ; free virtual = 371227
update_compile_order -fileset sources_1
open_bd_design {/home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd}
Reading block design file </home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd>...
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_100M
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.4 - zynq_ultra_ps_e_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_3
Adding component instance block -- xilinx.com:ip:system_management_wiz:1.3 - system_management_wiz_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_1
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_2
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_3
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_4
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_5
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_6
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_7
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_8
Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_9
Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_2
Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_0
Adding component instance block -- xilinx.com:ip:axi_uart16550:2.0 - axi_uart16550_1
Adding component instance block -- user.org:user:PWM_w_Int:1.0 - PWM_w_Int_1
Adding component instance block -- user.org:user:PWM_w_Int:1.0 - PWM_w_Int_0
Adding component instance block -- ecelrc:user:Capture_Timer:1.0 - Capture_Timer_0
Adding component instance block -- ecelrc:user:SHA3_BURST_MASTER:1.0 - SHA3_BURST_MASTER_0
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_1
Successfully read diagram <ultra96v2_oob> from block design file </home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd>
validate_bd_design
INFO: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: SmartConnect ultra96v2_oob_smartconnect_1_0 is in Low-Area Mode.
WARNING: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: IP ultra96v2_oob_smartconnect_1_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S00_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received.
WARNING: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: IP ultra96v2_oob_smartconnect_1_0 is configured in Low-area mode as all propagated traffic is low-bandwidth (AXI4LITE). SI S01_AXI has property HAS_BURST == 1. WRAP bursts are not supported in Low-area mode and will result in DECERR if received.
WARNING: [xilinx.com:ip:smartconnect:1.0-1] ultra96v2_oob_smartconnect_1_0: If WRAP transactions are required then turn off Low-area mode using ADVANCED_PROPERTIES. Execute following: set_property CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {disable_low_area_mode 1}} [get_bd_cells /ultra96v2_oob_smartconnect_1_0]
WARNING: [BD 41-237] Bus Interface property WUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /SHA3_BURST_MASTER_0/M00_AXI(1)
WARNING: [BD 41-237] Bus Interface property RUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /SHA3_BURST_MASTER_0/M00_AXI(1)
WARNING: [BD 41-237] Bus Interface property BUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_LPD(0) and /SHA3_BURST_MASTER_0/M00_AXI(1)
WARNING: [BD 41-927] Following properties on pin /ULTRA96_IO/SYS_MGMT/system_management_wiz_0/s_axi_aclk have been updated from connected ip, but BD cell '/ULTRA96_IO/SYS_MGMT/system_management_wiz_0' does not accept parameter changes, so they may not be synchronized with cell properties:
	FREQ_HZ = 250000000 
Please resolve any mismatches by directly setting properties on BD cell </ULTRA96_IO/SYS_MGMT/system_management_wiz_0> to completely resolve these warnings.
validate_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 7943.258 ; gain = 0.000 ; free physical = 200517 ; free virtual = 371015
report_ip_status -name ip_status 
set_property range 4K [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_SHA3_BURST_MASTER_0_S00_AXI_reg}]
set_property offset 0x00A0050000 [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_SHA3_BURST_MASTER_0_S00_AXI_reg}]
delete_bd_objs [get_bd_addr_segs zynq_ultra_ps_e_0/Data/SEG_SHA3_BURST_MASTER_0_S00_AXI_reg]
assign_bd_address -target_address_space /zynq_ultra_ps_e_0/Data [get_bd_addr_segs SHA3_BURST_MASTER_0/S00_AXI/S00_AXI_reg] -force
Slave segment '/SHA3_BURST_MASTER_0/S00_AXI/S00_AXI_reg' is being assigned into address space '/zynq_ultra_ps_e_0/Data' at <0xA005_0000 [ 64K ]>.
set_property range 4K [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_SHA3_BURST_MASTER_0_S00_AXI_reg}]
set_property offset 0x00B0000000 [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_SHA3_BURST_MASTER_0_S00_AXI_reg}]
save_bd_design
WARNING: [BD 41-2671] The dangling interface net <m00_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m01_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m02_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m03_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m04_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m05_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m06_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m07_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m08_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m09_aw_node_M_AXIS_ARB> will not be written out to the BD file.
WARNING: [BD 41-2671] The dangling interface net <m10_aw_node_M_AXIS_ARB> will not be written out to the BD file.
Wrote  : </home/projects/courses/spring_24/ee382n4-17365/arch/labs/vivado/SP2024/LAB_3/SHA3_2022.2/ultra96v2_oob.srcs/sources_1/bd/ultra96v2_oob/ultra96v2_oob.bd> 
exit
INFO: [Common 17-206] Exiting Vivado at Mon Feb 26 15:26:46 2024...