ecelrc user bus_timer 1.0 S00_AXI AWADDR s00_axi_awaddr AWPROT s00_axi_awprot AWVALID s00_axi_awvalid AWREADY s00_axi_awready WDATA s00_axi_wdata WSTRB s00_axi_wstrb WVALID s00_axi_wvalid WREADY s00_axi_wready BRESP s00_axi_bresp BVALID s00_axi_bvalid BREADY s00_axi_bready ARADDR s00_axi_araddr ARPROT s00_axi_arprot ARVALID s00_axi_arvalid ARREADY s00_axi_arready RDATA s00_axi_rdata RRESP s00_axi_rresp RVALID s00_axi_rvalid RREADY s00_axi_rready WIZ_DATA_WIDTH 32 WIZ_NUM_REG 4 SUPPORTS_NARROW_BURST 0 S00_AXI_RST RST s00_axi_aresetn POLARITY ACTIVE_LOW S00_AXI_CLK CLK s00_axi_aclk ASSOCIATED_BUSIF S00_AXI ASSOCIATED_RESET s00_axi_aresetn S00_AXI S00_AXI_reg 0 4096 32 register OFFSET_BASE_PARAM C_S00_AXI_BASEADDR OFFSET_HIGH_PARAM C_S00_AXI_HIGHADDR xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog bus_timer_v1_0 xilinx_verilogsynthesis_view_fileset viewChecksum e6e9c1ca xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog bus_timer_v1_0 xilinx_verilogbehavioralsimulation_view_fileset viewChecksum e6e9c1ca xilinx_softwaredriver Software Driver :vivado.xilinx.com:sw.driver xilinx_softwaredriver_view_fileset viewChecksum f6c688e4 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum fd592ead bd_tcl Block Diagram :vivado.xilinx.com:block.diagram bd_tcl_view_fileset viewChecksum 45a2f450 BRAM_read_start_arready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation BRAM_read_start_arvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation BRAM_write_start_awready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation BRAM_write_start_awvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation OCM_read_start_arready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation OCM_read_start_arvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation OCM_write_start_awready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation OCM_write_start_awvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_awaddr in 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_awprot in 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_awvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_awready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_wdata in 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_wstrb in 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_wvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_wready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_bresp out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_bvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_bready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_araddr in 3 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_arprot in 2 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_arvalid in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_arready out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rdata out 31 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rresp out 1 0 wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rvalid out wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_rready in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_aclk in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation s00_axi_aresetn in wire xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 4 choice_list_6fc15197 32 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW choice_pairs_ce1226b1 1 0 xilinx_verilogsynthesis_view_fileset hdl/bus_timer_v1_0_S00_AXI.v verilogSource hdl/bus_timer_v1_0.v verilogSource CHECKSUM_91d3e942 xilinx_verilogbehavioralsimulation_view_fileset hdl/bus_timer_v1_0_S00_AXI.v verilogSource hdl/bus_timer_v1_0.v verilogSource xilinx_softwaredriver_view_fileset drivers/bus_timer_v1_0/data/bus_timer.mdd mdd driver_mdd drivers/bus_timer_v1_0/data/bus_timer.tcl tclSource driver_tcl drivers/bus_timer_v1_0/src/Makefile driver_src drivers/bus_timer_v1_0/src/bus_timer.h cSource driver_src drivers/bus_timer_v1_0/src/bus_timer.c cSource driver_src drivers/bus_timer_v1_0/src/bus_timer_selftest.c cSource driver_src xilinx_xpgui_view_fileset xgui/bus_timer_v1_0.tcl tclSource CHECKSUM_fd592ead XGUI_VERSION_2 bd_tcl_view_fileset bd/bd.tcl tclSource My new AXI IP C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 false C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 4 false C_S00_AXI_BASEADDR C S00 AXI BASEADDR 0xFFFFFFFF false C_S00_AXI_HIGHADDR C S00 AXI HIGHADDR 0x00000000 false Component_Name bus_timer_v1_0 zynquplus AXI_Peripheral bus_timer_v1.0 5 2022-03-31T03:27:42Z /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 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/misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 /misc/scratch/mshah/LAB_3_Temp/ip_repo/bus_timer_1.0 2018.3