Spring 2011: EE 382N-4

Advanced Embedded Systems Architecture

Lab Assignment #3: Due Apr 25, 2011

 

 

Expected Outcome of this Lab: Perform a continuous memory test of the Block RAMs in the FPGA while dynamically varying the ARM system clock.

 

Note: This is a group lab exercise and every group should demonstrate the working of the code on the board. A team can have a maximum of two members.

 

 

 

Specification:

 

There are 32 individual Block RAM (BRAM) modules in the FPGA on the baseboard. For this lab you will be configuring all of the BRAMs into a single contiguous 32 wide RAM module. The RAM module will be mapped into the ARM processor address space using Chip Select #1.  The RAM module will support WORD addressing only.

 

The frequency needs to be changed to different frequencies (224, 240, 32, 128, 256) MHz while continuously performing the memory test on the RAM module.. Note that when the frequency changes the serial port frequency will also change, hence the hyper-terminal will not work. You need to change the serial port setting such that the hyper-terminal works. The details about the clock control registers can be found in chapter 6 of MC9328MX21RM.pdf.    The assembly language source code the sets up the clocks in uMon is located at rom_reset.S   Use this as guide.

 

 

 

 

Implementation details:

 

1)   Modify the mx21_gpio device driver code to do the following:

a.    Modify the address range such that it falls in the PLL, clock and reset control registers.

b.    Provide functions to read and write into the various clock control registers.

 

2)   Write a memory test that runs in Linux to test the RAM module in the FPGA. You can reuse the memory tester code you developed in Lab #1 if it was written to be called as a sub-routine in C. Otherwise write it in C.

a.   Randomly vary the data (32 bits) while randomly varying the address. Use a linear feedback shift register (LFSR) to generate the address and the data patterns.

b.   Change the frequency of the system clock by writing into the clock control registers. The clock frequencies are 224, 240, 32, 128 and 256 MHz Change other settings such that the hyper-terminal works (does not crash).  Measure the time it takes to perform a complete memory test for each clock frequency. This is accomplished using the jiffies we talked about in class.

 

c.    Repeat these steps for the five target frequencies. The Linux system should not crash when you change the clock frequency. You should be able to run this test for 15 minutes without any issues.

 

      3)  There are two ways to build the contiguous RAM array.

                  a.   Use the CoreGen tool in ISE. It will do the work of instantiating all of the BRAMS into a single "core". 

                       The core is then instantiated into your top.v module.  NOTE: CoreGen can generate modules that don't work so be careful when

                        using it.

 

                   b. The other way to build a contiguous RAM module is to instantiate the BRAMs as shown in the  top.v from the Demo in Lab #2.

                        In either case it is best to use the FPGA framework from Lab #2 to build the interface to RAM module.

 

Note: There is a very useful memory test built into uMon which can be used to check your RAM module once it is constructed. The user manual for uMon is located at umon_manual.pdf.   

 

 

Deliverables: The code (user application, device driver, Makefile, top.v) and your report must be zipped and submitted through the assignment section of Blackboard. Please refrain from sending them as attachments through email.