/* ---------------------core synthesis-----------------------*/

//This part is used to set the libraries. You must change these setting to
proper library in your environment
target_library =  /autofs/polaris/jaa/mosis/aci/sc/synopsys/typical.db 
symbol_library = /autofs/polaris/jaa/mosis/aci/sc/symbols/synopsys/tsmc18.sdb
synthetic_library =
/usr/local/packages/synopsys/libraries/syn/dw_foundation.sldb
link_library = "*" + synthetic_library + target_library


//read in the verilog design
read -format verilog add2.v     

//current_design is supposed to be your top module
current_design add 

//no error, maybe some warnings
check_design 

//link library to the design
link

//no wire load model in wire delay caculation
auto_wire_load_selection = false 

//If you instantiate the same module more than once, use it
uniquify 


//delay constraints
/*set_max_delay 0 -from all_inputs() -to all_outputs()*/

//area  constraints
set_max_area 0

//set top design
current_design add 


//synthesis
compile

//write out verilog netlist
write -f verilog -h -o add2_postsyn.v

//write out db format netlist
write -f db -h -o add2_postsyn.db