Spring 2006

 

EE 382V – System on Chip

 

LAB #2

 

DEADLINE 11:59pm, Mar 5th (Sunday)

 

0. NOTICE

             - Please use the discussion board of Blackborad (https://courses.utexas.edu/webapps/portal/frameset.jsp) for Q&A.

             - All reports/codes MUST be submitted to the Digital DropBox of Blackboard.

 

1. Overview

The Goal of this lab is to

1)        Understand floating point to fixed point conversion.

2)        Understand an interface between Hardware accelerator and AMBA bus.

3)        Understand an architecture of Viterbi decoder

 

The Assignment of this lab includes the following.

1)          Creating a behavior level / fixed point version of Viterbi decoder in SystemC.

2)          Implementing a HAL of the Viterbi decoder to interconnect to the AMBA bus.

3)          Integrating the Viterbi decoder into platform with a HAL to the AMBA bus.

 

2. LAB

 1) Tutorials

             a) Floating point 2 Fixed point

                          A floating point algorithm needs to be converted into fixed point algorithm for HW development.

                          This example shows how to do floating point–fixed point conversion in C/C++.

 

                          Also, you may test a fixed point version of soclab1 by following below steps

A.       Download new MySoftware.cpp.

B.        Overwrite old MySoftware.cpp(which is in soclab1/ut_example/build) with new MySoftware.cpp.

C.        Compile MySoftware.cpp again.

D.       Re-run ConvergenSC simulation.

 

b) AMBA bus interface

             Soclab1 example of LAB1 shows how to interface with AMBA bus and how to handle the data in/out.

             Please refer to following materials to learn more about AMBA bus APIs.
             A.   3. Transaction Level Modeling of coware online tutorial
             B.   TLM API Manual
             C.   AMBA bus library

 

c) Platform for LAB2

            Since soclab1 example has too small memory space to load DRM, you need a new platform.

            Download soclab2.tar.gz.

            It has new ROM and RAM with larger memory space and DISPLAY module is modified to display the current number of clock cycles.

            You may run  ../soclab2/example/top/drm to get brief idea and verify output by running %> diff viterbi_output viterbi_output.gold

            WARNING! It may take long time (~30min) depending on the machine load.

 

d) DRM source codes

            To accomplish LAB requirements, you had better to be familiar with DRM architecture and source codes.

            Remember the best reference is the block diagram of DRM.

            However, you should pay attention to the following source files.

           

            mlc-1.2.4_arm/common/GUI-QT/main.cpp      :    main() function is here.

            mlc-1.2.4_arm/common/DrmReceiver.cpp       :    The outmost loop for data processing is here. You can easily find MSCMLC decoder as well.

            mlc-1.2.4_arm/linux/irq.c                                :    ISR routine is here.
            mlc-1.2.4_arm/common/mlc/MLC.cpp, MLC.h  :    MSCMLC implementation is here.

            mlc-1.2.4_arm/common/mlc/ViteterbiDercoder.cpp, ViteterbiDercoder.cpp

                                                                                    :    Viterbi decoder implementation is here.

            mlc-1.2.4_arm/common/util/Modul.h              :    Templates for MLC receiver module is here.

 

 2) Viterbi decoder

             A part of DRM system, a stand-alone MSCMLC decoder is available with a golden input and output data.

This MSCMLC decoder calls viterbi decoder internally which should be implemented as HW for performance improvement.

Please follow the steps.

A.       Download MSCMLC decoder(mlc-1.2.4_arm.tar.gz) and study the interface to viterbi decoder.

B.        Make viterbi decoder as your own function with the simplest interface.

C.        Change all floating point variables in viterbi decoder into fixed point variables.

D.       Modify MSCMLC decoder such that all the arguments to viterbi decoder are fixed point variables (refer to tutorial a) .

       REMEMBER THAT SystemC simulation is slow. Please make sure your code doesn't have any bug with ARMSD (%>armsd).

   

E.        Create a SystemC module of viterbi decoder and use behavioral level description (use a C++ code as it is).

       REMEMBER THAT ConvergenSC simulation is even slower. Please make sure your code doesn't have any bug.

       If I were you, I'll do the following

        a) create a SystemC viterbi decoder module.

        b) create a testbench module to stress viterbi decoder. It may need to read some data from dump file.

        c) make a stand-alone program and configure viterbi decoder and testbench in sc_main().

        d) compile with g++ and verify viterbi decoder.

              

F.         Implement a HAL to AMBA bus with Coware AMBA bus APIs (refer to tutorial b) ).

G.        Define a memory-mapped interface between MSCMLC decoder and your own viterbi decoder SystemC module as in soclab1.

H.       Compile MSCMLC decoder with ARM compiler&linker (take advantage of makefile in soclab1).

I.         Open soclab2 in Platform Creator (%>pct) and add your viterbi decoder SystemC module (you need to import it).

J.         Make connections to complete platform design.

K.        Run an exported design on SystemC Shell (%>scsh).

L.        Confirm the functional equivalence (your output should be the same as the golden output).

 

Please assume that any operation (read-in from AMBA, write to AMBA and any computation) of viterbi decoder can be done in ONE cycle (which in turn means that your module should be clock-synchronized) temporarily (in LAB3, this will not be true any more).

            

3. Submission

 

 

Relevant Web Pages

Viterbi decoder

Visual Viterbi Decoder Simulation

 

                  DMA

                  Introduction to DMA

Altera DMA Controller for AHB (fact sheet)

AMBA Bus DMA Controller for the Leon processor