Spring 2008

 

EE 382V – SoC Design

 

LAB #4

 

To be assigned 00:01am - Mar 31 (Monday)

DEADLINE 11:59pm – April 20 (Sunday)

 

 

NOTICE

1.     This lab will be an class exercise and will be graded as part of the class project

2.      Please use the discussion board of blackboard or the email list for Q&A

3.      All reports and code MUST be submitted to the digital assignment of blackboard.

4.      Please check relevant web pages.

 

 

1.0 Overview: 

The goals of this lab are to:

，            Use the hardware accelerator(FPGA) to improve the performance of the viterbi decode function

 

The assignment of this lab includes the following.

，            Convert C2R raw verilog of viterbi decoder to FPGA friendly verilog

，            The software should have the Hardware Abstraction Layer (HAL) interface to interact with the FPGA

，            Use the development board (TLL6219) to run and co-verify the SoC viterbi decode function

，            The software should read the inputs from input file(s), call the hardware viterbi function with these inputs, get the output and print it onto console (or) to a file

 

 

2.0 Resources and tutorials

 

a)    The viterbi decoder verilog file should be obtained from the previous lab

a)    The inputs to the viterbi function are ip1_1, ip2_1 and punc_ip1

b)    The development board (TLL6219) has a Xilinx SPARTAN 3 FPGA and an ARM9 processor which will be used for the project

c)     Tutorials

，         Xilinx ISE: http://direct.xilinx.com/direct/ise9_tutorials/ise9tut.pdf

，         Overview of the board: /scratch/Documentation/TLL6219_Getting_Started_Manual_ver2.2_28Dec2007.pdf

，         Writing applications on the ARM platform: /scratch/Documentation/MC9328MX21RM.pdf (page 87 for memory map)

d)    Files for FPGA, original_top.v, top.ucf (usage will be explained in the next section)

 

 

3.0 Example: This example takes two integers as inputs and gives their sum as the output. The addition takes place in the FPGA which is called from the software.

 

a)    Software part

，         Download the example zip file into your directory

，         Do the following steps to unzip and compile the code

o        tar zvxf software_example.tar.gz

o        cd software_example

o        source /scratch/arm_linux_setup.sh

o        make

，         The makefile uses arm-linux-gcc to compile the code and arm-linux-strip to eliminate the unnecessary libraries

，         When compiled with `make` , will produce the `example` executable which can be run on the ARM board

，         HAL

o        In example.c, we have the HAL

o        The HAL consists of the addresses (addr0 to 2) and the corresponding code to access these addresses

o        The comments in example.c explain the process of sending the data through the HAL to the board and reading the result back to the software

o        The hardware described in 3.0.b will return the sum of the values in addr1 and addr2 whenever addr0 is read by the software. The HAL makes use of this setup to perform the addition.

 

b)    Hardware part

，         The hardware will read the values in addr1 and addr2, perform the addition and return the result, whenever addr0 is read by the software

，         top.v performs this functionality

o        This file is a modified version of original_top.v given in section 2.0.e

o        The state machine in original_top.v is modified to perform the addition process

，         STATE 6 performs the addition

，         We use Xilinx ISE for the synthesis and the generation of bit file which can then be downloaded to the FPGA. Here are the steps to working with the ISE.

o        Create a new project with following properties

，         Family: Spartan3

，         Device: XC3S1500

，         Package: FG676

，         Speed: -4

o        After clicking next twice, in the `Add existing Sources` tab, add both top.v and top.ucf files from your directory

，         Once you `finish` creating the project, you will see several small windows. In the `Processes` window, under `Generate Programming File`, double-click on `Programming File Generation Report`. This will synthesize, implement and finally generate the bit file.

，         The bit file (top.bit) will be generated in your project directory

 

c)     Combining both the software and the hardware (this needs to be performed in the ENS first floor lab, with the board)

1.     After the bit file is generated from the previous step, use Xilinx iMPACT to download it onto the board

a.     In the Xilinx ISE, under `Generate Programming File`, double-click on `Configure Device (iMPACT)`

b.     Retain the default values in the dialog box and click `Finish`

c.      Press the `Cancel` option on all the three dialog boxes that follow. This is very important or you might erase/overwrite stuff on the components of the board.

d.     Right-click on the xc3s1500 device. It will ask for a new configuration file, select the bit file that was generated in 3.0.b

e.     Select the xc3s1500 device and double-click on the `Program` option in the `Processes` window

                                                                                          i.      Click on `Ok` in the dialog box that appears, retaining the default options. You should now see a `Program Succeeded` message displayed

 

2.     This step involves pages 7 to 11 of the pdf document /scratch/Documentation/TLL6219_Getting_Started_Manual_ver2.2_28Dec2007.pdf

a.     Perform the steps in page 7 till 11

                                                                                          i.      This will power-on the board and start the HyperTerminal for communication with the ARM board.

b.     Type `startlinux` in the HyperTerminal

                                                                                          i.      This will bootup bare-bone linux (busybox) on the ARM processor

                                                                                        ii.      Use the `wget` command to download the software part which is the `example` executable into the filesystem from some public space

，         For eg. `wget http://www.cerc.utexas.edu/~rvemu/example`

 

3.     Now we have successfully setup the environment (hardware for running the software)

a.     In the HyperTerminal, go to the directory where you downloaded the `example`  executable

b.     Change permissions by doing a `chmod +x example`

c.      Do a `./example arg1 arg2` to execute the program. You should see the sum of arg1 and arg2 displayed on the console

 

 

                                                

4.0             Exercise

 

In lines with the example stated above, write the software that reads the input files from the file system and calls the viterbi decoder hardware with these inputs. Also the software should print the result obtained from the viterbi decoder hardware on to the console.

 

 

5.0 Lab report submission and demonstration

 

Submit your report to Blackboard. The report must include the verilog files and the `C` software. The class as a whole will be giving a demo on April 20th during the Sunday meeting session from 2pm till 4pm.