Assume clock runs at 100MHz (10ns).

 1) read-in from AMBA bus.
 	a) Esitmate the time to process a read-in from AMBA bus (data from AMBA to HW accelerator).
 	b) Caculate the # of cycles for this operation.
 	c) Whenever HW accelerator encounts this operation, add # of cycles of b) as a delay intentionally.
 2) write to AMBA bus.
 	a) Esitmate the time to process a write a data to AMBA bus (data from HW accelerator to AMBA).
 	b) Caculate the # of cycles for this operation.
 	c) Whenever HW accelerator encounts this operation, add # of cycles of b) as a delay intentionally.
 
 Please refer the following code.


 SC_MODULE(viterbi_dec)
 {
 	 int readin_delay;

	 SC_CTOR(viterbi_dec)
         {
           SC_METHOD (onclk);
           sensitive << clk.pos();
           dont_initialize();
         }
         
     	 void onclk()
         {
		if(readin_delay>0)
		{	
			readin_delay--;
			return;
		}
		else
		{
			//read-in operation is done!			
		}
         }
         
         void read-in()
         {
         	readin_delay = 5;
         	//do read-in operation.
         }
}